Commit 3a36f2ef authored by Eilon Greenstein's avatar Eilon Greenstein Committed by David S. Miller
Browse files

bnx2x: Removing CL73 code 



This code is disabled, so removing it to avoid confusion

Signed-off-by: default avatarYaniv Rosner <yanivr@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c1b73990

drivers/net/bnx2x_link.c

+19 −92
Original line number Diff line number Diff line
@@ -29,7 +29,6 @@ 
#include "bnx2x.h"



/********************************************************/

#define SUPPORT_CL73 0 /* Currently no */

#define ETH_HLEN			14

#define ETH_OVREHEAD		(ETH_HLEN + 8)/* 8 for CRC + VLAN*/

#define ETH_MIN_PACKET_SIZE		60
@@ -1208,62 +1207,9 @@ static void bnx2x_set_autoneg(struct link_params *params, 
			      MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,

			      reg_val);



	/* Enable Clause 73 Aneg */

	if ((vars->line_speed == SPEED_AUTO_NEG) &&

	    (SUPPORT_CL73)) {

		/* Enable BAM Station Manager */



		CL45_WR_OVER_CL22(bp, params->port,

				      params->phy_addr,

				      MDIO_REG_BANK_CL73_USERB0,

				      MDIO_CL73_USERB0_CL73_BAM_CTRL1,

				   (MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |

			MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |

			MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN));



		/* Merge CL73 and CL37 aneg resolution */

		CL45_RD_OVER_CL22(bp, params->port,

				      params->phy_addr,

				      MDIO_REG_BANK_CL73_USERB0,

				      MDIO_CL73_USERB0_CL73_BAM_CTRL3,

				      &reg_val);



		CL45_WR_OVER_CL22(bp, params->port,

				      params->phy_addr,

			MDIO_REG_BANK_CL73_USERB0,

			MDIO_CL73_USERB0_CL73_BAM_CTRL3,

			(reg_val |

			MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR));



		/* Set the CL73 AN speed */



		CL45_RD_OVER_CL22(bp, params->port,

				      params->phy_addr,

				      MDIO_REG_BANK_CL73_IEEEB1,

				      MDIO_CL73_IEEEB1_AN_ADV2, &reg_val);

		/* In the SerDes we support only the 1G.

		   In the XGXS we support the 10G KX4

		   but we currently do not support the KR */

		if (vars->phy_flags & PHY_XGXS_FLAG) {

			DP(NETIF_MSG_LINK, "XGXS\n");

			/* 10G KX4 */

			reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;

		} else {

			DP(NETIF_MSG_LINK, "SerDes\n");

			/* 1000M KX */

			reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;

		}

		CL45_WR_OVER_CL22(bp, params->port,

				      params->phy_addr,

				      MDIO_REG_BANK_CL73_IEEEB1,

				      MDIO_CL73_IEEEB1_AN_ADV2, reg_val);



		/* CL73 Autoneg Enabled */

		reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;

	} else {

	/* CL73 Autoneg Disabled */

	reg_val = 0;

	}



	CL45_WR_OVER_CL22(bp, params->port,

			      params->phy_addr,

			      MDIO_REG_BANK_CL73_IEEEB0,
@@ -1396,27 +1342,9 @@ static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params, 
static void bnx2x_restart_autoneg(struct link_params *params)

{

	struct bnx2x *bp = params->bp;

	u16 mii_control;

	DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");

	if (SUPPORT_CL73) {

		/* enable and restart clause 73 aneg */

		u16 an_ctrl;



		CL45_RD_OVER_CL22(bp, params->port,

				      params->phy_addr,

				      MDIO_REG_BANK_CL73_IEEEB0,

				      MDIO_CL73_IEEEB0_CL73_AN_CONTROL,

				  &an_ctrl);

		CL45_WR_OVER_CL22(bp, params->port,

				      params->phy_addr,

				MDIO_REG_BANK_CL73_IEEEB0,

				MDIO_CL73_IEEEB0_CL73_AN_CONTROL,

				(an_ctrl |

				MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |

				MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));



	} else {

	/* Enable and restart BAM/CL37 aneg */

		u16 mii_control;



	CL45_RD_OVER_CL22(bp, params->port,

			      params->phy_addr,
@@ -1434,7 +1362,6 @@ static void bnx2x_restart_autoneg(struct link_params *params) 
			       MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |

			       MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));

}

}



static void bnx2x_initialize_sgmii_process(struct link_params *params,

					 struct link_vars *vars)