Commit 386e75a4 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: split out gem/i915_gem_tiling.h from i915_drv.h

parent db583eea
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+1 −0
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@@ -12,6 +12,7 @@
#include "i915_gem_ioctls.h"
#include "i915_gem_mman.h"
#include "i915_gem_object.h"
#include "i915_gem_tiling.h"

/**
 * DOC: buffer object tiling
+18 −0
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/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2022 Intel Corporation
 */

#ifndef __I915_GEM_TILING_H__
#define __I915_GEM_TILING_H__

#include <linux/types.h>

struct drm_i915_private;

u32 i915_gem_fence_size(struct drm_i915_private *i915, u32 size,
			unsigned int tiling, unsigned int stride);
u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
			     unsigned int tiling, unsigned int stride);

#endif /* __I915_GEM_TILING_H__ */
+0 −5
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@@ -1715,11 +1715,6 @@ static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec
		i915_gem_object_is_tiled(obj);
}

u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
			unsigned int tiling, unsigned int stride);
u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
			     unsigned int tiling, unsigned int stride);

const char *i915_cache_level_str(struct drm_i915_private *i915, int type);

/* intel_device_info.c */
+1 −1
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@@ -26,8 +26,8 @@
#include <drm/drm_gem.h>

#include "display/intel_frontbuffer.h"

#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_tiling.h"
#include "gt/intel_engine.h"
#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_gt.h"