Commit 37139da1 authored by Bart Van Assche's avatar Bart Van Assche Committed by Martin K. Petersen
Browse files

scsi: qla2xxx: Fix the code that reads from mailbox registers

Make the MMIO accessors strongly typed such that the compiler checks
whether the accessor function is used that matches the register width. Fix
those MMIO accesses where another number of bits was read or written than
the size of the register.

Link: https://lore.kernel.org/r/20200518211712.11395-11-bvanassche@acm.org


Cc: Nilesh Javali <njavali@marvell.com>
Cc: Quinn Tran <qutran@marvell.com>
Cc: Martin Wilck <mwilck@suse.com>
Cc: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: default avatarDaniel Wagner <dwagner@suse.de>
Reviewed-by: default avatarHimanshu Madhani <himanshu.madhani@oracle.com>
Reviewed-by: default avatarHannes Reinecke <hare@suse.de>
Signed-off-by: default avatarBart Van Assche <bvanassche@acm.org>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent c3888416
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+44 −9
Original line number Diff line number Diff line
@@ -128,15 +128,50 @@ static inline uint32_t make_handle(uint16_t x, uint16_t y)
 * I/O register
*/

#define RD_REG_BYTE(addr)		readb(addr)
#define RD_REG_WORD(addr)		readw(addr)
#define RD_REG_DWORD(addr)		readl(addr)
#define RD_REG_BYTE_RELAXED(addr)	readb_relaxed(addr)
#define RD_REG_WORD_RELAXED(addr)	readw_relaxed(addr)
#define RD_REG_DWORD_RELAXED(addr)	readl_relaxed(addr)
#define WRT_REG_BYTE(addr, data)	writeb(data, addr)
#define WRT_REG_WORD(addr, data)	writew(data, addr)
#define WRT_REG_DWORD(addr, data)	writel(data, addr)
static inline u8 RD_REG_BYTE(const volatile u8 __iomem *addr)
{
	return readb(addr);
}

static inline u16 RD_REG_WORD(const volatile __le16 __iomem *addr)
{
	return readw(addr);
}

static inline u32 RD_REG_DWORD(const volatile __le32 __iomem *addr)
{
	return readl(addr);
}

static inline u8 RD_REG_BYTE_RELAXED(const volatile u8 __iomem *addr)
{
	return readb_relaxed(addr);
}

static inline u16 RD_REG_WORD_RELAXED(const volatile __le16 __iomem *addr)
{
	return readw_relaxed(addr);
}

static inline u32 RD_REG_DWORD_RELAXED(const volatile __le32 __iomem *addr)
{
	return readl_relaxed(addr);
}

static inline void WRT_REG_BYTE(volatile u8 __iomem *addr, u8 data)
{
	return writeb(data, addr);
}

static inline void WRT_REG_WORD(volatile __le16 __iomem *addr, u16 data)
{
	return writew(data, addr);
}

static inline void WRT_REG_DWORD(volatile __le32 __iomem *addr, u32 data)
{
	return writel(data, addr);
}

/*
 * ISP83XX specific remote register addresses
+3 −3
Original line number Diff line number Diff line
@@ -2219,7 +2219,7 @@ qla2x00_initialize_adapter(scsi_qla_host_t *vha)

	/* Check for secure flash support */
	if (IS_QLA28XX(ha)) {
		if (RD_REG_DWORD(&reg->mailbox12) & BIT_0)
		if (RD_REG_WORD(&reg->mailbox12) & BIT_0)
			ha->flags.secure_adapter = 1;
		ql_log(ql_log_info, vha, 0xffff, "Secure Adapter: %s\n",
		    (ha->flags.secure_adapter) ? "Yes" : "No");
@@ -2780,7 +2780,7 @@ qla24xx_reset_risc(scsi_qla_host_t *vha)
	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
	    "HCCR: 0x%x, MailBox0 Status 0x%x\n",
	    RD_REG_DWORD(&reg->hccr),
	    RD_REG_DWORD(&reg->mailbox0));
	    RD_REG_WORD(&reg->mailbox0));

	/* Wait for soft-reset to complete. */
	RD_REG_DWORD(&reg->ctrl_status);
@@ -4098,7 +4098,7 @@ qla24xx_config_rings(struct scsi_qla_host *vha)
	}

	/* PCI posting */
	RD_REG_DWORD(&ioreg->hccr);
	RD_REG_WORD(&ioreg->hccr);
}

/**
+1 −1
Original line number Diff line number Diff line
@@ -2268,7 +2268,7 @@ __qla2x00_alloc_iocbs(struct qla_qpair *qpair, srb_t *sp)
		    IS_QLA28XX(ha))
			cnt = RD_REG_DWORD(&reg->isp25mq.req_q_out);
		else if (IS_P3P_TYPE(ha))
			cnt = RD_REG_DWORD(&reg->isp82.req_q_out);
			cnt = RD_REG_DWORD(reg->isp82.req_q_out);
		else if (IS_FWI2_CAPABLE(ha))
			cnt = RD_REG_DWORD(&reg->isp24.req_q_out);
		else if (IS_QLAFX00(ha))
+2 −2
Original line number Diff line number Diff line
@@ -452,7 +452,7 @@ qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
	int rval;
	struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
	struct device_reg_82xx __iomem *reg82 = &vha->hw->iobase->isp82;
	uint16_t __iomem *wptr;
	__le16 __iomem *wptr;
	uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];

	/* Seed data -- mailbox1 -> mailbox7. */
@@ -3164,7 +3164,7 @@ qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
{
	uint16_t	cnt;
	uint32_t	mboxes;
	uint16_t __iomem *wptr;
	__le16 __iomem *wptr;
	struct qla_hw_data *ha = vha->hw;
	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;

+1 −1
Original line number Diff line number Diff line
@@ -106,7 +106,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
	uint8_t		io_lock_on;
	uint16_t	command = 0;
	uint16_t	*iptr;
	uint16_t __iomem *optr;
	__le16 __iomem  *optr;
	uint32_t	cnt;
	uint32_t	mboxes;
	unsigned long	wait_time;
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