Commit 36959e21 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r9a07g044: Add OPP table 



Add OPP table for RZ/G2L SoC.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211124154316.28365-1-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 7744b393

arch/arm64/boot/dts/renesas/r9a07g044.dtsi

+31 −0
Original line number Diff line number Diff line
@@ -42,6 +42,33 @@ extal_clk: extal { 
		clock-frequency = <0>;

	};



	cluster0_opp: opp-table-0 {

		compatible = "operating-points-v2";

		opp-shared;



		opp-150000000 {

			opp-hz = /bits/ 64 <150000000>;

			opp-microvolt = <1100000>;

			clock-latency-ns = <300000>;

		};

		opp-300000000 {

			opp-hz = /bits/ 64 <300000000>;

			opp-microvolt = <1100000>;

			clock-latency-ns = <300000>;

		};

		opp-600000000 {

			opp-hz = /bits/ 64 <600000000>;

			opp-microvolt = <1100000>;

			clock-latency-ns = <300000>;

		};

		opp-1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <1100000>;

			clock-latency-ns = <300000>;

			opp-suspend;

		};

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -63,6 +90,8 @@ cpu0: cpu@0 { 
			device_type = "cpu";

			next-level-cache = <&L3_CA55>;

			enable-method = "psci";

			clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;

			operating-points-v2 = <&cluster0_opp>;

		};



		cpu1: cpu@100 {
@@ -71,6 +100,8 @@ cpu1: cpu@100 { 
			device_type = "cpu";

			next-level-cache = <&L3_CA55>;

			enable-method = "psci";

			clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;

			operating-points-v2 = <&cluster0_opp>;

		};



		L3_CA55: cache-controller-0 {