Loading drivers/scsi/hpsa.c +0 −3 Original line number Diff line number Diff line Loading @@ -6932,7 +6932,6 @@ static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) * the 5 lower bits of the address are used by the hardware. and by * the driver. See comments in hpsa.h for more info. */ #define COMMANDLIST_ALIGNMENT 128 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT); h = kzalloc(sizeof(*h), GFP_KERNEL); if (!h) Loading Loading @@ -7405,7 +7404,6 @@ static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h) * because the 7 lower bits of the address are used by the * hardware. */ #define IOACCEL1_COMMANDLIST_ALIGNMENT 128 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) % IOACCEL1_COMMANDLIST_ALIGNMENT); h->ioaccel_cmd_pool = Loading Loading @@ -7443,7 +7441,6 @@ static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h) if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES) h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES; #define IOACCEL2_COMMANDLIST_ALIGNMENT 128 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) % IOACCEL2_COMMANDLIST_ALIGNMENT); h->ioaccel2_cmd_pool = Loading drivers/scsi/hpsa_cmd.h +6 −27 Original line number Diff line number Diff line Loading @@ -375,6 +375,7 @@ struct ctlr_info; /* defined in hpsa.h */ * or a bus address. */ #define COMMANDLIST_ALIGNMENT 128 struct CommandList { struct CommandListHeader Header; struct RequestBlock Request; Loading @@ -389,21 +390,7 @@ struct CommandList { struct list_head list; struct completion *waiting; void *scsi_cmd; /* on 64 bit architectures, to get this to be 32-byte-aligned * it so happens we need PAD_64 bytes of padding, on 32 bit systems, * we need PAD_32 bytes of padding (see below). This does that. * If it happens that 64 bit and 32 bit systems need different * padding, PAD_32 and PAD_64 can be set independently, and. * the code below will do the right thing. */ #define IS_32_BIT ((8 - sizeof(long))/4) #define IS_64_BIT (!IS_32_BIT) #define PAD_32 (40) #define PAD_64 (12) #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64) u8 pad[COMMANDLIST_PAD]; }; } __aligned(COMMANDLIST_ALIGNMENT); /* Max S/G elements in I/O accelerator command */ #define IOACCEL1_MAXSGENTRIES 24 Loading @@ -413,6 +400,7 @@ struct CommandList { * Structure for I/O accelerator (mode 1) commands. * Note that this structure must be 128-byte aligned in size. */ #define IOACCEL1_COMMANDLIST_ALIGNMENT 128 struct io_accel1_cmd { u16 dev_handle; /* 0x00 - 0x01 */ u8 reserved1; /* 0x02 */ Loading Loading @@ -440,12 +428,7 @@ struct io_accel1_cmd { struct vals32 host_addr; /* 0x70 - 0x77 */ u8 CISS_LUN[8]; /* 0x78 - 0x7F */ struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES]; #define IOACCEL1_PAD_64 0 #define IOACCEL1_PAD_32 0 #define IOACCEL1_PAD (IS_32_BIT * IOACCEL1_PAD_32 + \ IS_64_BIT * IOACCEL1_PAD_64) u8 pad[IOACCEL1_PAD]; }; } __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT); #define IOACCEL1_FUNCTION_SCSIIO 0x00 #define IOACCEL1_SGLOFFSET 32 Loading Loading @@ -510,14 +493,11 @@ struct io_accel2_scsi_response { u8 sense_data_buff[32]; /* sense/response data buffer */ }; #define IOACCEL2_64_PAD 76 #define IOACCEL2_32_PAD 76 #define IOACCEL2_PAD (IS_32_BIT * IOACCEL2_32_PAD + \ IS_64_BIT * IOACCEL2_64_PAD) /* * Structure for I/O accelerator (mode 2 or m2) commands. * Note that this structure must be 128-byte aligned in size. */ #define IOACCEL2_COMMANDLIST_ALIGNMENT 128 struct io_accel2_cmd { u8 IU_type; /* IU Type */ u8 direction; /* direction, memtype, and encryption */ Loading @@ -544,8 +524,7 @@ struct io_accel2_cmd { u32 tweak_upper; /* Encryption tweak, upper 4 bytes */ struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES]; struct io_accel2_scsi_response error_data; u8 pad[IOACCEL2_PAD]; }; } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT); /* * defines for Mode 2 command struct Loading Loading
drivers/scsi/hpsa.c +0 −3 Original line number Diff line number Diff line Loading @@ -6932,7 +6932,6 @@ static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) * the 5 lower bits of the address are used by the hardware. and by * the driver. See comments in hpsa.h for more info. */ #define COMMANDLIST_ALIGNMENT 128 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT); h = kzalloc(sizeof(*h), GFP_KERNEL); if (!h) Loading Loading @@ -7405,7 +7404,6 @@ static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h) * because the 7 lower bits of the address are used by the * hardware. */ #define IOACCEL1_COMMANDLIST_ALIGNMENT 128 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) % IOACCEL1_COMMANDLIST_ALIGNMENT); h->ioaccel_cmd_pool = Loading Loading @@ -7443,7 +7441,6 @@ static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h) if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES) h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES; #define IOACCEL2_COMMANDLIST_ALIGNMENT 128 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) % IOACCEL2_COMMANDLIST_ALIGNMENT); h->ioaccel2_cmd_pool = Loading
drivers/scsi/hpsa_cmd.h +6 −27 Original line number Diff line number Diff line Loading @@ -375,6 +375,7 @@ struct ctlr_info; /* defined in hpsa.h */ * or a bus address. */ #define COMMANDLIST_ALIGNMENT 128 struct CommandList { struct CommandListHeader Header; struct RequestBlock Request; Loading @@ -389,21 +390,7 @@ struct CommandList { struct list_head list; struct completion *waiting; void *scsi_cmd; /* on 64 bit architectures, to get this to be 32-byte-aligned * it so happens we need PAD_64 bytes of padding, on 32 bit systems, * we need PAD_32 bytes of padding (see below). This does that. * If it happens that 64 bit and 32 bit systems need different * padding, PAD_32 and PAD_64 can be set independently, and. * the code below will do the right thing. */ #define IS_32_BIT ((8 - sizeof(long))/4) #define IS_64_BIT (!IS_32_BIT) #define PAD_32 (40) #define PAD_64 (12) #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64) u8 pad[COMMANDLIST_PAD]; }; } __aligned(COMMANDLIST_ALIGNMENT); /* Max S/G elements in I/O accelerator command */ #define IOACCEL1_MAXSGENTRIES 24 Loading @@ -413,6 +400,7 @@ struct CommandList { * Structure for I/O accelerator (mode 1) commands. * Note that this structure must be 128-byte aligned in size. */ #define IOACCEL1_COMMANDLIST_ALIGNMENT 128 struct io_accel1_cmd { u16 dev_handle; /* 0x00 - 0x01 */ u8 reserved1; /* 0x02 */ Loading Loading @@ -440,12 +428,7 @@ struct io_accel1_cmd { struct vals32 host_addr; /* 0x70 - 0x77 */ u8 CISS_LUN[8]; /* 0x78 - 0x7F */ struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES]; #define IOACCEL1_PAD_64 0 #define IOACCEL1_PAD_32 0 #define IOACCEL1_PAD (IS_32_BIT * IOACCEL1_PAD_32 + \ IS_64_BIT * IOACCEL1_PAD_64) u8 pad[IOACCEL1_PAD]; }; } __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT); #define IOACCEL1_FUNCTION_SCSIIO 0x00 #define IOACCEL1_SGLOFFSET 32 Loading Loading @@ -510,14 +493,11 @@ struct io_accel2_scsi_response { u8 sense_data_buff[32]; /* sense/response data buffer */ }; #define IOACCEL2_64_PAD 76 #define IOACCEL2_32_PAD 76 #define IOACCEL2_PAD (IS_32_BIT * IOACCEL2_32_PAD + \ IS_64_BIT * IOACCEL2_64_PAD) /* * Structure for I/O accelerator (mode 2 or m2) commands. * Note that this structure must be 128-byte aligned in size. */ #define IOACCEL2_COMMANDLIST_ALIGNMENT 128 struct io_accel2_cmd { u8 IU_type; /* IU Type */ u8 direction; /* direction, memtype, and encryption */ Loading @@ -544,8 +524,7 @@ struct io_accel2_cmd { u32 tweak_upper; /* Encryption tweak, upper 4 bytes */ struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES]; struct io_accel2_scsi_response error_data; u8 pad[IOACCEL2_PAD]; }; } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT); /* * defines for Mode 2 command struct Loading