Commit 3591be2e authored by Christoph Niedermaier's avatar Christoph Niedermaier Committed by Shawn Guo
Browse files

ARM: dts: imx6qdl-dhcom: Move IPU iomux node from PDK2 to SoM file 

The SoM itself provides the display interface, see [1] page 20.
Those pins have to be used as the RGB/DPI interface or not used
at all. So rather than duplicate the pinmux settings in every
carrier board DT, better move them into the SoM DTSI.

[1] https://wiki.dh-electronics.com/images/2/2e/DOC_DHCOM-Standard-Specification_R01_2016-11-17.pdf



Signed-off-by: default avatarChristoph Niedermaier <cniedermaier@dh-electronics.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 7e4bf4d8

arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi

+0 −33
Original line number Diff line number Diff line
@@ -332,37 +332,4 @@ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */ 
			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0xb1 /* Int */

		>;

	};



	pinctrl_ipu1_lcdif: ipu1-lcdif-grp {

		fsl,pins = <

			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0x38

			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0x38

			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0x38

			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x38

			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0x38

			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x38

			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x38

			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0x38

			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0x38

			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0x38

			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0x38

			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0x38

			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0x38

			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0x38

			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0x38

			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0x38

			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0x38

			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0x38

			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0x38

			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0x38

			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0x38

			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0x38

			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18	0x38

			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19	0x38

			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20	0x38

			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21	0x38

			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22	0x38

			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23	0x38

		>;

	};

};

arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi

+33 −0
Original line number Diff line number Diff line
@@ -667,6 +667,39 @@ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 
		>;

	};



	pinctrl_ipu1_lcdif: ipu1-lcdif-grp {

		fsl,pins = <

			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0x38

			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0x38

			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0x38

			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x38

			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0x38

			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x38

			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x38

			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0x38

			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0x38

			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0x38

			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0x38

			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0x38

			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0x38

			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0x38

			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0x38

			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0x38

			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0x38

			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0x38

			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0x38

			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0x38

			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0x38

			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0x38

			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18	0x38

			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19	0x38

			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20	0x38

			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21	0x38

			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22	0x38

			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23	0x38

		>;

	};



	pinctrl_pcie: pcie-grp {

		fsl,pins = <

			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x1b0b1 /* Wake */