Commit 3408a95f authored by Tony Lindgren's avatar Tony Lindgren
Browse files

ARM: dts: Group omap3 CM_FCLKEN1_CORE clocks 



The clksel related registers on omap3 cause unique_unit_address and
node_name_chars_strict warnings with the W=1 or W=2 make flags enabled.

With the clock drivers updated, we can now avoid most of these warnings
by grouping the TI component clocks using the TI clksel binding, and
with the use of clock-output-names property to avoid non-standard node
names for the clocks.

Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 1e7079d3

arch/arm/boot/dts/am35xx-clocks.dtsi

+13 −6
Original line number Diff line number Diff line
@@ -90,14 +90,21 @@ uart4_ick_am35xx: uart4_ick_am35xx@a10 { 
		ti,bit-shift = <23>;

	};



	uart4_fck_am35xx: uart4_fck_am35xx@a00 {

	clock@a00 {

		compatible = "ti,clksel";

		reg = <0xa00>;

		#clock-cells = <2>;

		#address-cells = <0>;



		uart4_fck_am35xx: clock-uart4-fck-am35xx {

			#clock-cells = <0>;

			compatible = "ti,wait-gate-clock";

			clock-output-names = "uart4_fck_am35xx";

			clocks = <&core_48m_fck>;

		reg = <0x0a00>;

			ti,bit-shift = <23>;

		};

	};

};



&cm_clockdomains {

	core_l3_clkdm: core_l3_clkdm {

arch/arm/boot/dts/omap3430es1-clocks.dtsi

+29 −22
Original line number Diff line number Diff line
@@ -46,28 +46,35 @@ gfx_cg2_ck: gfx_cg2_ck@b00 { 
		ti,bit-shift = <2>;

	};



	d2d_26m_fck: d2d_26m_fck@a00 {

	clock@a00 {

		compatible = "ti,clksel";

		reg = <0xa00>;

		#clock-cells = <2>;

		#address-cells = <0>;



		d2d_26m_fck: clock-d2d-26m-fck {

			#clock-cells = <0>;

			compatible = "ti,wait-gate-clock";

			clock-output-names = "d2d_26m_fck";

			clocks = <&sys_ck>;

		reg = <0x0a00>;

			ti,bit-shift = <3>;

		};



	fshostusb_fck: fshostusb_fck@a00 {

		fshostusb_fck: clock-fshostusb-fck {

			#clock-cells = <0>;

			compatible = "ti,wait-gate-clock";

			clock-output-names = "fshostusb_fck";

			clocks = <&core_48m_fck>;

		reg = <0x0a00>;

			ti,bit-shift = <5>;

		};



	ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 {

		ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 {

			#clock-cells = <0>;

			compatible = "ti,composite-no-wait-gate-clock";

			clock-output-names = "ssi_ssr_gate_fck_3430es1";

			clocks = <&corex2_fck>;

			ti,bit-shift = <0>;

		reg = <0x0a00>;

		};

	};



	ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 {

arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi

+21 −14
Original line number Diff line number Diff line
@@ -187,14 +187,28 @@ iva2_ck: iva2_ck@0 { 
		ti,bit-shift = <0>;

	};



	modem_fck: modem_fck@a00 {

	clock@a00 {

		compatible = "ti,clksel";

		reg = <0xa00>;

		#clock-cells = <2>;

		#address-cells = <0>;



		modem_fck: clock-modem-fck {

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "modem_fck";

			clocks = <&sys_ck>;

		reg = <0x0a00>;

			ti,bit-shift = <31>;

		};



		mspro_fck: clock-mspro-fck {

			#clock-cells = <0>;

			compatible = "ti,wait-gate-clock";

			clock-output-names = "mspro_fck";

			clocks = <&core_96m_fck>;

			ti,bit-shift = <23>;

		};

	};

	sad2d_ick: sad2d_ick@a10 {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";
@@ -211,13 +225,6 @@ mad2d_ick: mad2d_ick@a18 { 
		ti,bit-shift = <3>;

	};



	mspro_fck: mspro_fck@a00 {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&core_96m_fck>;

		reg = <0x0a00>;

		ti,bit-shift = <23>;

	};

};



&cm_clockdomains {

arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi

+13 −6
Original line number Diff line number Diff line
@@ -149,13 +149,20 @@ mmchs3_ick: mmchs3_ick@a10 { 
		ti,bit-shift = <30>;

	};



	mmchs3_fck: mmchs3_fck@a00 {

	clock@a00 {

		compatible = "ti,clksel";

		reg = <0xa00>;

		#clock-cells = <2>;

		#address-cells = <0>;



		mmchs3_fck: clock-mmchs3-fck {

			#clock-cells = <0>;

			compatible = "ti,wait-gate-clock";

			clock-output-names = "mmchs3_fck";

			clocks = <&core_96m_fck>;

		reg = <0x0a00>;

			ti,bit-shift = <30>;

		};

	};



	dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 {

		#clock-cells = <0>;

arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi

+13 −6
Original line number Diff line number Diff line
@@ -5,12 +5,19 @@ 
 * Copyright (C) 2013 Texas Instruments, Inc.

 */

&cm_clocks {

	ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {

	clock@a00 {

		compatible = "ti,clksel";

		reg = <0xa00>;

		#clock-cells = <2>;

		#address-cells = <0>;



		ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 {

			#clock-cells = <0>;

			compatible = "ti,composite-no-wait-gate-clock";

			clock-output-names = "ssi_ssr_gate_fck_3430es2";

			clocks = <&corex2_fck>;

			ti,bit-shift = <0>;

		reg = <0x0a00>;

		};

	};



	ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {