Commit 32932281 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/bar: convert to new-style nvkm_subdev 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent ef8bc576

drivers/gpu/drm/nouveau/include/nvif/device.h

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ u64 nvif_device_time(struct nvif_device *); 
#define nvxx_bios(a) nvkm_bios(nvxx_device(a))

#define nvxx_fb(a) nvkm_fb(nvxx_device(a))

#define nvxx_mmu(a) nvkm_mmu(nvxx_device(a))

#define nvxx_bar(a) nvkm_bar(nvxx_device(a))

#define nvxx_bar(a) nvxx_device(a)->bar

#define nvxx_gpio(a) nvkm_gpio(nvxx_device(a))

#define nvxx_clk(a) nvkm_clk(nvxx_device(a))

#define nvxx_i2c(a) nvkm_i2c(nvxx_device(a))

drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h

+9 −13
Original line number Diff line number Diff line 
#ifndef __NVKM_BAR_H__

#define __NVKM_BAR_H__

#include <core/subdev.h>

struct nvkm_mem;

struct nvkm_vma;



struct nvkm_bar {

	const struct nvkm_bar_func *func;

	struct nvkm_subdev subdev;



	struct nvkm_vm *(*kmap)(struct nvkm_bar *);

	int  (*umap)(struct nvkm_bar *, u64 size, int type, struct nvkm_vma *);

	void (*unmap)(struct nvkm_bar *, struct nvkm_vma *);

	void (*flush)(struct nvkm_bar *);

	spinlock_t lock;



	/* whether the BAR supports to be ioremapped WC or should be uncached */

	bool iomap_uncached;

};



static inline struct nvkm_bar *

nvkm_bar(void *obj)

{

	return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_BAR);

}

void nvkm_bar_flush(struct nvkm_bar *);

struct nvkm_vm *nvkm_bar_kmap(struct nvkm_bar *);

int nvkm_bar_umap(struct nvkm_bar *, u64 size, int type, struct nvkm_vma *);



extern struct nvkm_oclass nv50_bar_oclass;

extern struct nvkm_oclass gf100_bar_oclass;

extern struct nvkm_oclass gk20a_bar_oclass;

int nv50_bar_new(struct nvkm_device *, int, struct nvkm_bar **);

int g84_bar_new(struct nvkm_device *, int, struct nvkm_bar **);

int gf100_bar_new(struct nvkm_device *, int, struct nvkm_bar **);

int gk20a_bar_new(struct nvkm_device *, int, struct nvkm_bar **);

#endif

drivers/gpu/drm/nouveau/nouveau_bo.c

+4 −5
Original line number Diff line number Diff line
@@ -1392,7 +1392,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 
			if (drm->device.info.family >= NV_DEVICE_INFO_V0_FERMI)

				page_shift = node->page_shift;



			ret = bar->umap(bar, node->size << 12, page_shift,

			ret = nvkm_bar_umap(bar, node->size << 12, page_shift,

					    &node->bar_vma);

			if (ret)

				return ret;
@@ -1410,14 +1410,13 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 
static void

nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)

{

	struct nouveau_drm *drm = nouveau_bdev(bdev);

	struct nvkm_bar *bar = nvxx_bar(&drm->device);

	struct nvkm_mem *node = mem->mm_node;



	if (!node->bar_vma.node)

		return;



	bar->unmap(bar, &node->bar_vma);

	nvkm_vm_unmap(&node->bar_vma);

	nvkm_vm_put(&node->bar_vma);

}



static int

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+35 −35
Original line number Diff line number Diff line
@@ -778,7 +778,7 @@ nv4e_chipset = { 
static const struct nvkm_device_chip

nv50_chipset = {

	.name = "G80",

//	.bar = nv50_bar_new,

	.bar = nv50_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = nv50_bus_new,

//	.clk = nv50_clk_new,
@@ -881,7 +881,7 @@ nv68_chipset = { 
static const struct nvkm_device_chip

nv84_chipset = {

	.name = "G84",

//	.bar = nv50_bar_new,

	.bar = g84_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = nv50_bus_new,

//	.clk = g84_clk_new,
@@ -912,7 +912,7 @@ nv84_chipset = { 
static const struct nvkm_device_chip

nv86_chipset = {

	.name = "G86",

//	.bar = nv50_bar_new,

	.bar = g84_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = nv50_bus_new,

//	.clk = g84_clk_new,
@@ -943,7 +943,7 @@ nv86_chipset = { 
static const struct nvkm_device_chip

nv92_chipset = {

	.name = "G92",

//	.bar = nv50_bar_new,

	.bar = g84_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = nv50_bus_new,

//	.clk = g84_clk_new,
@@ -974,7 +974,7 @@ nv92_chipset = { 
static const struct nvkm_device_chip

nv94_chipset = {

	.name = "G94",

//	.bar = nv50_bar_new,

	.bar = g84_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = g94_bus_new,

//	.clk = g84_clk_new,
@@ -1019,7 +1019,7 @@ nv96_chipset = { 
//	.fb = g84_fb_new,

//	.imem = nv50_instmem_new,

//	.mmu = nv50_mmu_new,

//	.bar = nv50_bar_new,

	.bar = g84_bar_new,

//	.volt = nv40_volt_new,

//	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,
@@ -1050,7 +1050,7 @@ nv98_chipset = { 
//	.fb = g84_fb_new,

//	.imem = nv50_instmem_new,

//	.mmu = nv50_mmu_new,

//	.bar = nv50_bar_new,

	.bar = g84_bar_new,

//	.volt = nv40_volt_new,

//	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,
@@ -1067,7 +1067,7 @@ nv98_chipset = { 
static const struct nvkm_device_chip

nva0_chipset = {

	.name = "GT200",

//	.bar = nv50_bar_new,

	.bar = g84_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = g94_bus_new,

//	.clk = g84_clk_new,
@@ -1098,7 +1098,7 @@ nva0_chipset = { 
static const struct nvkm_device_chip

nva3_chipset = {

	.name = "GT215",

//	.bar = nv50_bar_new,

	.bar = g84_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = g94_bus_new,

//	.clk = gt215_clk_new,
@@ -1131,7 +1131,7 @@ nva3_chipset = { 
static const struct nvkm_device_chip

nva5_chipset = {

	.name = "GT216",

//	.bar = nv50_bar_new,

	.bar = g84_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = g94_bus_new,

//	.clk = gt215_clk_new,
@@ -1163,7 +1163,7 @@ nva5_chipset = { 
static const struct nvkm_device_chip

nva8_chipset = {

	.name = "GT218",

//	.bar = nv50_bar_new,

	.bar = g84_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = g94_bus_new,

//	.clk = gt215_clk_new,
@@ -1195,7 +1195,7 @@ nva8_chipset = { 
static const struct nvkm_device_chip

nvaa_chipset = {

	.name = "MCP77/MCP78",

//	.bar = nv50_bar_new,

	.bar = g84_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = g94_bus_new,

//	.clk = mcp77_clk_new,
@@ -1226,7 +1226,7 @@ nvaa_chipset = { 
static const struct nvkm_device_chip

nvac_chipset = {

	.name = "MCP79/MCP7A",

//	.bar = nv50_bar_new,

	.bar = g84_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = g94_bus_new,

//	.clk = mcp77_clk_new,
@@ -1257,7 +1257,7 @@ nvac_chipset = { 
static const struct nvkm_device_chip

nvaf_chipset = {

	.name = "MCP89",

//	.bar = nv50_bar_new,

	.bar = g84_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = g94_bus_new,

//	.clk = gt215_clk_new,
@@ -1289,7 +1289,7 @@ nvaf_chipset = { 
static const struct nvkm_device_chip

nvc0_chipset = {

	.name = "GF100",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gf100_clk_new,
@@ -1324,7 +1324,7 @@ nvc0_chipset = { 
static const struct nvkm_device_chip

nvc1_chipset = {

	.name = "GF108",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gf100_clk_new,
@@ -1358,7 +1358,7 @@ nvc1_chipset = { 
static const struct nvkm_device_chip

nvc3_chipset = {

	.name = "GF106",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gf100_clk_new,
@@ -1392,7 +1392,7 @@ nvc3_chipset = { 
static const struct nvkm_device_chip

nvc4_chipset = {

	.name = "GF104",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gf100_clk_new,
@@ -1427,7 +1427,7 @@ nvc4_chipset = { 
static const struct nvkm_device_chip

nvc8_chipset = {

	.name = "GF110",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gf100_clk_new,
@@ -1462,7 +1462,7 @@ nvc8_chipset = { 
static const struct nvkm_device_chip

nvce_chipset = {

	.name = "GF114",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gf100_clk_new,
@@ -1497,7 +1497,7 @@ nvce_chipset = { 
static const struct nvkm_device_chip

nvcf_chipset = {

	.name = "GF116",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gf100_clk_new,
@@ -1531,7 +1531,7 @@ nvcf_chipset = { 
static const struct nvkm_device_chip

nvd7_chipset = {

	.name = "GF117",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gf100_clk_new,
@@ -1563,7 +1563,7 @@ nvd7_chipset = { 
static const struct nvkm_device_chip

nvd9_chipset = {

	.name = "GF119",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gf100_clk_new,
@@ -1597,7 +1597,7 @@ nvd9_chipset = { 
static const struct nvkm_device_chip

nve4_chipset = {

	.name = "GK104",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gk104_clk_new,
@@ -1633,7 +1633,7 @@ nve4_chipset = { 
static const struct nvkm_device_chip

nve6_chipset = {

	.name = "GK106",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gk104_clk_new,
@@ -1669,7 +1669,7 @@ nve6_chipset = { 
static const struct nvkm_device_chip

nve7_chipset = {

	.name = "GK107",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gk104_clk_new,
@@ -1705,7 +1705,7 @@ nve7_chipset = { 
static const struct nvkm_device_chip

nvea_chipset = {

	.name = "GK20A",

//	.bar = gk20a_bar_new,

	.bar = gk20a_bar_new,

//	.bus = gf100_bus_new,

//	.clk = gk20a_clk_new,

//	.fb = gk20a_fb_new,
@@ -1729,7 +1729,7 @@ nvea_chipset = { 
static const struct nvkm_device_chip

nvf0_chipset = {

	.name = "GK110",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gk104_clk_new,
@@ -1765,7 +1765,7 @@ nvf0_chipset = { 
static const struct nvkm_device_chip

nvf1_chipset = {

	.name = "GK110B",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gk104_clk_new,
@@ -1801,7 +1801,7 @@ nvf1_chipset = { 
static const struct nvkm_device_chip

nv106_chipset = {

	.name = "GK208B",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gk104_clk_new,
@@ -1836,7 +1836,7 @@ nv106_chipset = { 
static const struct nvkm_device_chip

nv108_chipset = {

	.name = "GK208",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gk104_clk_new,
@@ -1871,7 +1871,7 @@ nv108_chipset = { 
static const struct nvkm_device_chip

nv117_chipset = {

	.name = "GM107",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.clk = gk104_clk_new,
@@ -1901,7 +1901,7 @@ nv117_chipset = { 
static const struct nvkm_device_chip

nv124_chipset = {

	.name = "GM204",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.devinit = gm204_devinit_new,
@@ -1930,7 +1930,7 @@ nv124_chipset = { 
static const struct nvkm_device_chip

nv126_chipset = {

	.name = "GM206",

//	.bar = gf100_bar_new,

	.bar = gf100_bar_new,

//	.bios = nvkm_bios_new,

//	.bus = gf100_bus_new,

//	.devinit = gm204_devinit_new,
@@ -1959,7 +1959,7 @@ nv126_chipset = { 
static const struct nvkm_device_chip

nv12b_chipset = {

	.name = "GM20B",

//	.bar = gk20a_bar_new,

	.bar = gk20a_bar_new,

//	.bus = gf100_bus_new,

//	.fb = gk20a_fb_new,

//	.fuse = gm107_fuse_new,

drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c

+0 −9
Original line number Diff line number Diff line
@@ -44,7 +44,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gf100_ibus_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
@@ -76,7 +75,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gf100_ibus_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
@@ -108,7 +106,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gf100_ibus_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
@@ -139,7 +136,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gf100_ibus_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
@@ -171,7 +167,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gf100_ibus_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
@@ -202,7 +197,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gf100_ibus_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
@@ -233,7 +227,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gf100_ibus_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
@@ -265,7 +258,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gf100_ibus_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf110_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
@@ -296,7 +288,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gf100_ibus_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;