Commit 31c3af50 authored by Guennadi Liakhovetski's avatar Guennadi Liakhovetski Committed by Paul Mundt
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sh: support SIU sourcing from external clock on sh7722 



Implement .set_rate() for all SH "div4 clocks," .enable(), .disable(), and
.set_parent() for those, that support them. This allows, among other uses,
reparenting of SIU clocks to the external source, and enabling and
disabling of the IrDA clock on sh7722.

Signed-off-by: default avatarGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 14965f16

arch/sh/include/asm/clock.h

+4 −0
Original line number Diff line number Diff line
@@ -148,6 +148,10 @@ int sh_clk_mstp32_register(struct clk *clks, int nr); 


int sh_clk_div4_register(struct clk *clks, int nr,

			 struct clk_div_mult_table *table);

int sh_clk_div4_enable_register(struct clk *clks, int nr,

			 struct clk_div_mult_table *table);

int sh_clk_div4_reparent_register(struct clk *clks, int nr,

			 struct clk_div_mult_table *table);



#define SH_CLK_DIV6(_name, _parent, _reg, _flags)	\

{							\

arch/sh/kernel/cpu/clock-cpg.c

+91 −3
Original line number Diff line number Diff line
@@ -160,13 +160,81 @@ static unsigned long sh_clk_div4_recalc(struct clk *clk) 
	return clk->freq_table[idx].frequency;

}



static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)

{

	struct clk_div_mult_table *table = clk->priv;

	u32 value;

	int ret;



	if (!strcmp("pll_clk", parent->name))

		value = __raw_readl(clk->enable_reg) & ~(1 << 7);

	else

		value = __raw_readl(clk->enable_reg) | (1 << 7);



	ret = clk_reparent(clk, parent);

	if (ret < 0)

		return ret;



	__raw_writel(value, clk->enable_reg);



	/* Rebiuld the frequency table */

	clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,

			     table, &clk->arch_flags);



	return 0;

}



static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id)

{

	unsigned long value;

	int idx = clk_rate_table_find(clk, clk->freq_table, rate);

	if (idx < 0)

		return idx;



	value = __raw_readl(clk->enable_reg);

	value &= ~0xf;

	value |= idx;

	__raw_writel(value, clk->enable_reg);



	return 0;

}



static int sh_clk_div4_enable(struct clk *clk)

{

	__raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg);

	return 0;

}



static void sh_clk_div4_disable(struct clk *clk)

{

	__raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg);

}



static struct clk_ops sh_clk_div4_clk_ops = {

	.recalc		= sh_clk_div4_recalc,

	.set_rate	= sh_clk_div4_set_rate,

	.round_rate	= sh_clk_div_round_rate,

};



int __init sh_clk_div4_register(struct clk *clks, int nr,

				struct clk_div_mult_table *table)

static struct clk_ops sh_clk_div4_enable_clk_ops = {

	.recalc		= sh_clk_div4_recalc,

	.set_rate	= sh_clk_div4_set_rate,

	.round_rate	= sh_clk_div_round_rate,

	.enable		= sh_clk_div4_enable,

	.disable	= sh_clk_div4_disable,

};



static struct clk_ops sh_clk_div4_reparent_clk_ops = {

	.recalc		= sh_clk_div4_recalc,

	.set_rate	= sh_clk_div4_set_rate,

	.round_rate	= sh_clk_div_round_rate,

	.enable		= sh_clk_div4_enable,

	.disable	= sh_clk_div4_disable,

	.set_parent	= sh_clk_div4_set_parent,

};



static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,

			struct clk_div_mult_table *table, struct clk_ops *ops)

{

	struct clk *clkp;

	void *freq_table;
@@ -185,7 +253,7 @@ int __init sh_clk_div4_register(struct clk *clks, int nr, 
	for (k = 0; !ret && (k < nr); k++) {

		clkp = clks + k;



		clkp->ops = &sh_clk_div4_clk_ops;

		clkp->ops = ops;

		clkp->id = -1;

		clkp->priv = table;
@@ -198,6 +266,26 @@ int __init sh_clk_div4_register(struct clk *clks, int nr, 
	return ret;

}



int __init sh_clk_div4_register(struct clk *clks, int nr,

				struct clk_div_mult_table *table)

{

	return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops);

}



int __init sh_clk_div4_enable_register(struct clk *clks, int nr,

				struct clk_div_mult_table *table)

{

	return sh_clk_div4_register_ops(clks, nr, table,

					&sh_clk_div4_enable_clk_ops);

}



int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,

				struct clk_div_mult_table *table)

{

	return sh_clk_div4_register_ops(clks, nr, table,

					&sh_clk_div4_reparent_clk_ops);

}



#ifdef CONFIG_SH_CLK_CPG_LEGACY

static struct clk master_clk = {

	.name		= "master_clk",

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

+21 −4
Original line number Diff line number Diff line
@@ -117,12 +117,11 @@ static struct clk_div_mult_table div4_table = { 
	.nr_multipliers = ARRAY_SIZE(multipliers),

};



enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,

       DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR };



#define DIV4(_str, _reg, _bit, _mask, _flags) \

  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)



enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };



struct clk div4_clks[DIV4_NR] = {

	[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),

	[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
@@ -130,9 +129,19 @@ struct clk div4_clks[DIV4_NR] = { 
	[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),

};



enum { DIV4_IRDA, DIV4_ENABLE_NR };



struct clk div4_enable_clks[DIV4_ENABLE_NR] = {

	[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),

};



enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };



struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {

	[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),

	[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),

	[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),

};



struct clk div6_clks[] = {
@@ -188,6 +197,14 @@ int __init arch_clk_init(void) 
	if (!ret)

		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);



	if (!ret)

		ret = sh_clk_div4_enable_register(div4_enable_clks,

					DIV4_ENABLE_NR, &div4_table);



	if (!ret)

		ret = sh_clk_div4_reparent_register(div4_reparent_clks,

					DIV4_REPARENT_NR, &div4_table);



	if (!ret)

		ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));