Loading arch/powerpc/include/asm/mmu.h +5 −0 Original line number Diff line number Diff line Loading @@ -115,6 +115,11 @@ #ifndef __ASSEMBLY__ #include <asm/cputable.h> #ifdef CONFIG_PPC_FSL_BOOK3E #include <asm/percpu.h> DECLARE_PER_CPU(int, next_tlbcam_idx); #endif static inline int mmu_has_feature(unsigned long feature) { return (cur_cpu_spec->mmu_features & feature); Loading arch/powerpc/kernel/smp.c +4 −0 Original line number Diff line number Diff line Loading @@ -305,6 +305,10 @@ struct thread_info *current_set[NR_CPUS]; static void __devinit smp_store_cpu_info(int id) { per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); #ifdef CONFIG_PPC_FSL_BOOK3E per_cpu(next_tlbcam_idx, id) = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; #endif } void __init smp_prepare_cpus(unsigned int max_cpus) Loading arch/powerpc/mm/mem.c +9 −0 Original line number Diff line number Diff line Loading @@ -353,6 +353,15 @@ void __init mem_init(void) } #endif /* CONFIG_HIGHMEM */ #if defined(CONFIG_PPC_FSL_BOOK3E) && !defined(CONFIG_SMP) /* * If smp is enabled, next_tlbcam_idx is initialized in the cpu up * functions.... do it here for the non-smp case. */ per_cpu(next_tlbcam_idx, smp_processor_id()) = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; #endif printk(KERN_INFO "Memory: %luk/%luk available (%luk kernel code, " "%luk reserved, %luk data, %luk bss, %luk init)\n", nr_free_pages() << (PAGE_SHIFT-10), Loading arch/powerpc/mm/tlb_nohash.c +6 −0 Original line number Diff line number Diff line Loading @@ -102,6 +102,12 @@ unsigned long linear_map_top; /* Top of linear mapping */ #endif /* CONFIG_PPC64 */ #ifdef CONFIG_PPC_FSL_BOOK3E /* next_tlbcam_idx is used to round-robin tlbcam entry assignment */ DEFINE_PER_CPU(int, next_tlbcam_idx); EXPORT_PER_CPU_SYMBOL(next_tlbcam_idx); #endif /* * Base TLB flushing operations: * Loading Loading
arch/powerpc/include/asm/mmu.h +5 −0 Original line number Diff line number Diff line Loading @@ -115,6 +115,11 @@ #ifndef __ASSEMBLY__ #include <asm/cputable.h> #ifdef CONFIG_PPC_FSL_BOOK3E #include <asm/percpu.h> DECLARE_PER_CPU(int, next_tlbcam_idx); #endif static inline int mmu_has_feature(unsigned long feature) { return (cur_cpu_spec->mmu_features & feature); Loading
arch/powerpc/kernel/smp.c +4 −0 Original line number Diff line number Diff line Loading @@ -305,6 +305,10 @@ struct thread_info *current_set[NR_CPUS]; static void __devinit smp_store_cpu_info(int id) { per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); #ifdef CONFIG_PPC_FSL_BOOK3E per_cpu(next_tlbcam_idx, id) = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; #endif } void __init smp_prepare_cpus(unsigned int max_cpus) Loading
arch/powerpc/mm/mem.c +9 −0 Original line number Diff line number Diff line Loading @@ -353,6 +353,15 @@ void __init mem_init(void) } #endif /* CONFIG_HIGHMEM */ #if defined(CONFIG_PPC_FSL_BOOK3E) && !defined(CONFIG_SMP) /* * If smp is enabled, next_tlbcam_idx is initialized in the cpu up * functions.... do it here for the non-smp case. */ per_cpu(next_tlbcam_idx, smp_processor_id()) = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; #endif printk(KERN_INFO "Memory: %luk/%luk available (%luk kernel code, " "%luk reserved, %luk data, %luk bss, %luk init)\n", nr_free_pages() << (PAGE_SHIFT-10), Loading
arch/powerpc/mm/tlb_nohash.c +6 −0 Original line number Diff line number Diff line Loading @@ -102,6 +102,12 @@ unsigned long linear_map_top; /* Top of linear mapping */ #endif /* CONFIG_PPC64 */ #ifdef CONFIG_PPC_FSL_BOOK3E /* next_tlbcam_idx is used to round-robin tlbcam entry assignment */ DEFINE_PER_CPU(int, next_tlbcam_idx); EXPORT_PER_CPU_SYMBOL(next_tlbcam_idx); #endif /* * Base TLB flushing operations: * Loading