Commit 2e23a1db authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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arm64: dts: renesas: r8a774e1-hihope-rzg2h: Setup DU clocks

parent 112441c2
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+11 −0
Original line number Diff line number Diff line
@@ -24,3 +24,14 @@ memory@500000000 {
		reg = <0x5 0x00000000 0x0 0x80000000>;
	};
};

&du {
	clocks = <&cpg CPG_MOD 724>,
		 <&cpg CPG_MOD 723>,
		 <&cpg CPG_MOD 721>,
		 <&versaclock5 1>,
		 <&x302_clk>,
		 <&versaclock5 2>;
	clock-names = "du.0", "du.1", "du.3",
		      "dclkin.0", "dclkin.1", "dclkin.3";
};