Loading drivers/gpu/drm/nouveau/nouveau_drv.h +1 −0 Original line number Diff line number Diff line Loading @@ -1359,6 +1359,7 @@ int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); /* nv50_gpio.c */ int nv50_gpio_init(struct drm_device *dev); void nv50_gpio_fini(struct drm_device *dev); int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); Loading drivers/gpu/drm/nouveau/nouveau_irq.c +2 −4 Original line number Diff line number Diff line Loading @@ -1238,11 +1238,9 @@ nouveau_irq_handler(DRM_IRQ_ARGS) status &= ~NV_PMC_INTR_0_CRTCn_PENDING; } if (status & (NV_PMC_INTR_0_NV50_DISPLAY_PENDING | NV_PMC_INTR_0_NV50_I2C_PENDING)) { if (status & NV_PMC_INTR_0_NV50_DISPLAY_PENDING) { nv50_display_irq_handler(dev); status &= ~(NV_PMC_INTR_0_NV50_DISPLAY_PENDING | NV_PMC_INTR_0_NV50_I2C_PENDING); status &= ~NV_PMC_INTR_0_NV50_DISPLAY_PENDING; } for (i = 0; i < 32 && status; i++) { Loading drivers/gpu/drm/nouveau/nouveau_state.c +1 −1 Original line number Diff line number Diff line Loading @@ -393,7 +393,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) engine->display.init = nv50_display_init; engine->display.destroy = nv50_display_destroy; engine->gpio.init = nv50_gpio_init; engine->gpio.takedown = nouveau_stub_takedown; engine->gpio.takedown = nv50_gpio_fini; engine->gpio.get = nv50_gpio_get; engine->gpio.set = nv50_gpio_set; engine->gpio.irq_enable = nv50_gpio_irq_enable; Loading drivers/gpu/drm/nouveau/nv50_display.c +0 −19 Original line number Diff line number Diff line Loading @@ -869,25 +869,6 @@ nv50_display_irq_handler(struct drm_device *dev) struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t delayed = 0; if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) { uint32_t hpd0_bits, hpd1_bits = 0; hpd0_bits = nv_rd32(dev, 0xe054); nv_wr32(dev, 0xe054, hpd0_bits); if (dev_priv->chipset >= 0x90) { hpd1_bits = nv_rd32(dev, 0xe074); nv_wr32(dev, 0xe074, hpd1_bits); } spin_lock(&dev_priv->hpd_state.lock); dev_priv->hpd_state.hpd0_bits |= hpd0_bits; dev_priv->hpd_state.hpd1_bits |= hpd1_bits; spin_unlock(&dev_priv->hpd_state.lock); queue_work(dev_priv->wq, &dev_priv->hpd_work); } while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) { uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); Loading drivers/gpu/drm/nouveau/nv50_gpio.c +36 −0 Original line number Diff line number Diff line Loading @@ -26,6 +26,8 @@ #include "nouveau_drv.h" #include "nouveau_hw.h" static void nv50_gpio_isr(struct drm_device *dev); static int nv50_gpio_location(struct dcb_gpio_entry *gpio, uint32_t *reg, uint32_t *shift) { Loading Loading @@ -107,5 +109,39 @@ nv50_gpio_init(struct drm_device *dev) nv_wr32(dev, 0xe074, 0xffffffff); } nouveau_irq_register(dev, 21, nv50_gpio_isr); return 0; } void nv50_gpio_fini(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; nv_wr32(dev, 0xe050, 0x00000000); if (dev_priv->chipset >= 0x90) nv_wr32(dev, 0xe070, 0x00000000); nouveau_irq_unregister(dev, 21); } static void nv50_gpio_isr(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t hpd0_bits, hpd1_bits = 0; hpd0_bits = nv_rd32(dev, 0xe054); nv_wr32(dev, 0xe054, hpd0_bits); if (dev_priv->chipset >= 0x90) { hpd1_bits = nv_rd32(dev, 0xe074); nv_wr32(dev, 0xe074, hpd1_bits); } spin_lock(&dev_priv->hpd_state.lock); dev_priv->hpd_state.hpd0_bits |= hpd0_bits; dev_priv->hpd_state.hpd1_bits |= hpd1_bits; spin_unlock(&dev_priv->hpd_state.lock); queue_work(dev_priv->wq, &dev_priv->hpd_work); } Loading
drivers/gpu/drm/nouveau/nouveau_drv.h +1 −0 Original line number Diff line number Diff line Loading @@ -1359,6 +1359,7 @@ int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); /* nv50_gpio.c */ int nv50_gpio_init(struct drm_device *dev); void nv50_gpio_fini(struct drm_device *dev); int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); Loading
drivers/gpu/drm/nouveau/nouveau_irq.c +2 −4 Original line number Diff line number Diff line Loading @@ -1238,11 +1238,9 @@ nouveau_irq_handler(DRM_IRQ_ARGS) status &= ~NV_PMC_INTR_0_CRTCn_PENDING; } if (status & (NV_PMC_INTR_0_NV50_DISPLAY_PENDING | NV_PMC_INTR_0_NV50_I2C_PENDING)) { if (status & NV_PMC_INTR_0_NV50_DISPLAY_PENDING) { nv50_display_irq_handler(dev); status &= ~(NV_PMC_INTR_0_NV50_DISPLAY_PENDING | NV_PMC_INTR_0_NV50_I2C_PENDING); status &= ~NV_PMC_INTR_0_NV50_DISPLAY_PENDING; } for (i = 0; i < 32 && status; i++) { Loading
drivers/gpu/drm/nouveau/nouveau_state.c +1 −1 Original line number Diff line number Diff line Loading @@ -393,7 +393,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) engine->display.init = nv50_display_init; engine->display.destroy = nv50_display_destroy; engine->gpio.init = nv50_gpio_init; engine->gpio.takedown = nouveau_stub_takedown; engine->gpio.takedown = nv50_gpio_fini; engine->gpio.get = nv50_gpio_get; engine->gpio.set = nv50_gpio_set; engine->gpio.irq_enable = nv50_gpio_irq_enable; Loading
drivers/gpu/drm/nouveau/nv50_display.c +0 −19 Original line number Diff line number Diff line Loading @@ -869,25 +869,6 @@ nv50_display_irq_handler(struct drm_device *dev) struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t delayed = 0; if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) { uint32_t hpd0_bits, hpd1_bits = 0; hpd0_bits = nv_rd32(dev, 0xe054); nv_wr32(dev, 0xe054, hpd0_bits); if (dev_priv->chipset >= 0x90) { hpd1_bits = nv_rd32(dev, 0xe074); nv_wr32(dev, 0xe074, hpd1_bits); } spin_lock(&dev_priv->hpd_state.lock); dev_priv->hpd_state.hpd0_bits |= hpd0_bits; dev_priv->hpd_state.hpd1_bits |= hpd1_bits; spin_unlock(&dev_priv->hpd_state.lock); queue_work(dev_priv->wq, &dev_priv->hpd_work); } while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) { uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); Loading
drivers/gpu/drm/nouveau/nv50_gpio.c +36 −0 Original line number Diff line number Diff line Loading @@ -26,6 +26,8 @@ #include "nouveau_drv.h" #include "nouveau_hw.h" static void nv50_gpio_isr(struct drm_device *dev); static int nv50_gpio_location(struct dcb_gpio_entry *gpio, uint32_t *reg, uint32_t *shift) { Loading Loading @@ -107,5 +109,39 @@ nv50_gpio_init(struct drm_device *dev) nv_wr32(dev, 0xe074, 0xffffffff); } nouveau_irq_register(dev, 21, nv50_gpio_isr); return 0; } void nv50_gpio_fini(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; nv_wr32(dev, 0xe050, 0x00000000); if (dev_priv->chipset >= 0x90) nv_wr32(dev, 0xe070, 0x00000000); nouveau_irq_unregister(dev, 21); } static void nv50_gpio_isr(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t hpd0_bits, hpd1_bits = 0; hpd0_bits = nv_rd32(dev, 0xe054); nv_wr32(dev, 0xe054, hpd0_bits); if (dev_priv->chipset >= 0x90) { hpd1_bits = nv_rd32(dev, 0xe074); nv_wr32(dev, 0xe074, hpd1_bits); } spin_lock(&dev_priv->hpd_state.lock); dev_priv->hpd_state.hpd0_bits |= hpd0_bits; dev_priv->hpd_state.hpd1_bits |= hpd1_bits; spin_unlock(&dev_priv->hpd_state.lock); queue_work(dev_priv->wq, &dev_priv->hpd_work); }