Commit 2b77f199 authored by Ran Sun's avatar Ran Sun Committed by Alex Deucher
Browse files

drm/amdgpu: Clean up errors in dce_v10_0.c 



Fix the following errors reported by checkpatch:

ERROR: that open brace { should be on the previous line

Signed-off-by: default avatarRan Sun <sunran001@208suo.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7c29b402

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

+10 −20
Original line number Diff line number Diff line
@@ -52,8 +52,7 @@ 
static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);

static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);



static const u32 crtc_offsets[] =

{

static const u32 crtc_offsets[] = {

	CRTC0_REGISTER_OFFSET,

	CRTC1_REGISTER_OFFSET,

	CRTC2_REGISTER_OFFSET,
@@ -63,8 +62,7 @@ static const u32 crtc_offsets[] = 
	CRTC6_REGISTER_OFFSET

};



static const u32 hpd_offsets[] =

{

static const u32 hpd_offsets[] = {

	HPD0_REGISTER_OFFSET,

	HPD1_REGISTER_OFFSET,

	HPD2_REGISTER_OFFSET,
@@ -121,30 +119,26 @@ static const struct { 
	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK

} };



static const u32 golden_settings_tonga_a11[] =

{

static const u32 golden_settings_tonga_a11[] = {

	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,

	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,

	mmFBC_MISC, 0x1f311fff, 0x12300000,

	mmHDMI_CONTROL, 0x31000111, 0x00000011,

};



static const u32 tonga_mgcg_cgcg_init[] =

{

static const u32 tonga_mgcg_cgcg_init[] = {

	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,

	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,

};



static const u32 golden_settings_fiji_a10[] =

{

static const u32 golden_settings_fiji_a10[] = {

	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,

	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,

	mmFBC_MISC, 0x1f311fff, 0x12300000,

	mmHDMI_CONTROL, 0x31000111, 0x00000011,

};



static const u32 fiji_mgcg_cgcg_init[] =

{

static const u32 fiji_mgcg_cgcg_init[] = {

	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,

	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,

};
@@ -1425,8 +1419,7 @@ static void dce_v10_0_audio_enable(struct amdgpu_device *adev, 
			   enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);

}



static const u32 pin_offsets[] =

{

static const u32 pin_offsets[] = {

	AUD0_REGISTER_OFFSET,

	AUD1_REGISTER_OFFSET,

	AUD2_REGISTER_OFFSET,
@@ -1811,8 +1804,7 @@ static void dce_v10_0_afmt_fini(struct amdgpu_device *adev) 
	}

}



static const u32 vga_control_regs[6] =

{

static const u32 vga_control_regs[6] = {

	mmD1VGA_CONTROL,

	mmD2VGA_CONTROL,

	mmD3VGA_CONTROL,
@@ -3651,8 +3643,7 @@ static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev) 
	adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;

}



const struct amdgpu_ip_block_version dce_v10_0_ip_block =

{

const struct amdgpu_ip_block_version dce_v10_0_ip_block = {

	.type = AMD_IP_BLOCK_TYPE_DCE,

	.major = 10,

	.minor = 0,
@@ -3660,8 +3651,7 @@ const struct amdgpu_ip_block_version dce_v10_0_ip_block = 
	.funcs = &dce_v10_0_ip_funcs,

};



const struct amdgpu_ip_block_version dce_v10_1_ip_block =

{

const struct amdgpu_ip_block_version dce_v10_1_ip_block = {

	.type = AMD_IP_BLOCK_TYPE_DCE,

	.major = 10,

	.minor = 1,