Commit 2b6b29f3 authored by Srinivasan Shanmugam's avatar Srinivasan Shanmugam Committed by Alex Deucher
Browse files

drm/amdgpu: Fix complex macros error 



Fixes the below:

ERROR: Macros with complex values should be enclosed in parentheses

WARNING: macros should not use a trailing semicolon
+#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));

Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com>
Signed-off-by: default avatarSrinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent dc427a47

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −1
Original line number Diff line number Diff line
@@ -1321,7 +1321,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
	((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)

#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))



#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));

#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter))



#define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i))

#define for_each_inst(i, inst_mask)        \

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c

+1 −1
Original line number Diff line number Diff line
@@ -149,7 +149,7 @@ 
				       RAS_TABLE_HEADER_SIZE - \

				       RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE)



#define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev

#define to_amdgpu_device(x) ((container_of(x, struct amdgpu_ras, eeprom_control))->adev)



static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)

{

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ 
#define AMDGPU_VCN_MAX_ENC_RINGS	3



#define AMDGPU_MAX_VCN_INSTANCES	4

#define AMDGPU_MAX_VCN_ENC_RINGS  AMDGPU_VCN_MAX_ENC_RINGS * AMDGPU_MAX_VCN_INSTANCES

#define AMDGPU_MAX_VCN_ENC_RINGS  (AMDGPU_VCN_MAX_ENC_RINGS * AMDGPU_MAX_VCN_INSTANCES)



#define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)

#define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h

+4 −2
Original line number Diff line number Diff line
@@ -62,7 +62,9 @@ int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev); 
int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev);

void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev);



#define AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4

#define AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1

#define AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE \

	(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4)

#define AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE \

	(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1)



#endif