Commit 2a7909c0 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/disp: split user classes out from engine implementations 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 0710cc31

drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h

+0 −6
Original line number Diff line number Diff line
@@ -13,12 +13,6 @@ struct nvkm_disp { 
	struct nvkm_event vblank;

};



static inline struct nvkm_disp *

nvkm_disp(void *obj)

{

	return (void *)nvkm_engine(obj, NVDEV_ENGINE_DISP);

}



extern struct nvkm_oclass *nv04_disp_oclass;

extern struct nvkm_oclass *nv50_disp_oclass;

extern struct nvkm_oclass *g84_disp_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild

+47 −4
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ nvkm-y += nvkm/engine/disp/g84.o 
nvkm-y += nvkm/engine/disp/g94.o

nvkm-y += nvkm/engine/disp/gt200.o

nvkm-y += nvkm/engine/disp/gt215.o

nvkm-y += nvkm/engine/disp/gf110.o

nvkm-y += nvkm/engine/disp/gf119.o

nvkm-y += nvkm/engine/disp/gk104.o

nvkm-y += nvkm/engine/disp/gk110.o

nvkm-y += nvkm/engine/disp/gm107.o
@@ -17,18 +17,61 @@ nvkm-y += nvkm/engine/disp/dacnv50.o 
nvkm-y += nvkm/engine/disp/piornv50.o

nvkm-y += nvkm/engine/disp/sornv50.o

nvkm-y += nvkm/engine/disp/sorg94.o

nvkm-y += nvkm/engine/disp/sorgf110.o

nvkm-y += nvkm/engine/disp/sorgf119.o

nvkm-y += nvkm/engine/disp/sorgm204.o

nvkm-y += nvkm/engine/disp/dport.o



nvkm-y += nvkm/engine/disp/conn.o



nvkm-y += nvkm/engine/disp/hdagt215.o

nvkm-y += nvkm/engine/disp/hdagf110.o

nvkm-y += nvkm/engine/disp/hdagf119.o



nvkm-y += nvkm/engine/disp/hdmig84.o

nvkm-y += nvkm/engine/disp/hdmigt215.o

nvkm-y += nvkm/engine/disp/hdmigf110.o

nvkm-y += nvkm/engine/disp/hdmigf119.o

nvkm-y += nvkm/engine/disp/hdmigk104.o



nvkm-y += nvkm/engine/disp/vga.o



nvkm-y += nvkm/engine/disp/rootnv04.o

nvkm-y += nvkm/engine/disp/rootnv50.o

nvkm-y += nvkm/engine/disp/rootg84.o

nvkm-y += nvkm/engine/disp/rootg94.o

nvkm-y += nvkm/engine/disp/rootgt200.o

nvkm-y += nvkm/engine/disp/rootgt215.o

nvkm-y += nvkm/engine/disp/rootgf119.o

nvkm-y += nvkm/engine/disp/rootgk104.o

nvkm-y += nvkm/engine/disp/rootgk110.o

nvkm-y += nvkm/engine/disp/rootgm107.o

nvkm-y += nvkm/engine/disp/rootgm204.o



nvkm-y += nvkm/engine/disp/channv50.o

nvkm-y += nvkm/engine/disp/changf119.o



nvkm-y += nvkm/engine/disp/dmacnv50.o

nvkm-y += nvkm/engine/disp/dmacgf119.o



nvkm-y += nvkm/engine/disp/basenv50.o

nvkm-y += nvkm/engine/disp/baseg84.o

nvkm-y += nvkm/engine/disp/basegf119.o



nvkm-y += nvkm/engine/disp/corenv50.o

nvkm-y += nvkm/engine/disp/coreg84.o

nvkm-y += nvkm/engine/disp/coreg94.o

nvkm-y += nvkm/engine/disp/coregf119.o

nvkm-y += nvkm/engine/disp/coregk104.o



nvkm-y += nvkm/engine/disp/ovlynv50.o

nvkm-y += nvkm/engine/disp/ovlyg84.o

nvkm-y += nvkm/engine/disp/ovlygt200.o

nvkm-y += nvkm/engine/disp/ovlygf119.o

nvkm-y += nvkm/engine/disp/ovlygk104.o



nvkm-y += nvkm/engine/disp/piocnv50.o

nvkm-y += nvkm/engine/disp/piocgf119.o



nvkm-y += nvkm/engine/disp/cursnv50.o

nvkm-y += nvkm/engine/disp/cursgf119.o



nvkm-y += nvkm/engine/disp/oimmnv50.o

nvkm-y += nvkm/engine/disp/oimmgf119.o

drivers/gpu/drm/nouveau/nvkm/engine/disp/baseg84.c

0 → 100644
+65 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2012 Red Hat Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Ben Skeggs

 */

#include "dmacnv50.h"



static const struct nv50_disp_mthd_list

g84_disp_base_mthd_base = {

	.mthd = 0x0000,

	.addr = 0x000000,

	.data = {

		{ 0x0080, 0x000000 },

		{ 0x0084, 0x0008c4 },

		{ 0x0088, 0x0008d0 },

		{ 0x008c, 0x0008dc },

		{ 0x0090, 0x0008e4 },

		{ 0x0094, 0x610884 },

		{ 0x00a0, 0x6108a0 },

		{ 0x00a4, 0x610878 },

		{ 0x00c0, 0x61086c },

		{ 0x00c4, 0x610800 },

		{ 0x00c8, 0x61080c },

		{ 0x00cc, 0x610818 },

		{ 0x00e0, 0x610858 },

		{ 0x00e4, 0x610860 },

		{ 0x00e8, 0x6108ac },

		{ 0x00ec, 0x6108b4 },

		{ 0x00fc, 0x610824 },

		{ 0x0100, 0x610894 },

		{ 0x0104, 0x61082c },

		{ 0x0110, 0x6108bc },

		{ 0x0114, 0x61088c },

		{}

	}

};



const struct nv50_disp_mthd_chan

g84_disp_base_mthd_chan = {

	.name = "Base",

	.addr = 0x000540,

	.data = {

		{ "Global", 1, &g84_disp_base_mthd_base },

		{  "Image", 2, &nv50_disp_base_mthd_image },

		{}

	}

};

drivers/gpu/drm/nouveau/nvkm/engine/disp/basegf119.c

0 → 100644
+114 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2012 Red Hat Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Ben Skeggs

 */

#include "dmacnv50.h"



static const struct nv50_disp_mthd_list

gf119_disp_base_mthd_base = {

	.mthd = 0x0000,

	.addr = 0x000000,

	.data = {

		{ 0x0080, 0x661080 },

		{ 0x0084, 0x661084 },

		{ 0x0088, 0x661088 },

		{ 0x008c, 0x66108c },

		{ 0x0090, 0x661090 },

		{ 0x0094, 0x661094 },

		{ 0x00a0, 0x6610a0 },

		{ 0x00a4, 0x6610a4 },

		{ 0x00c0, 0x6610c0 },

		{ 0x00c4, 0x6610c4 },

		{ 0x00c8, 0x6610c8 },

		{ 0x00cc, 0x6610cc },

		{ 0x00e0, 0x6610e0 },

		{ 0x00e4, 0x6610e4 },

		{ 0x00e8, 0x6610e8 },

		{ 0x00ec, 0x6610ec },

		{ 0x00fc, 0x6610fc },

		{ 0x0100, 0x661100 },

		{ 0x0104, 0x661104 },

		{ 0x0108, 0x661108 },

		{ 0x010c, 0x66110c },

		{ 0x0110, 0x661110 },

		{ 0x0114, 0x661114 },

		{ 0x0118, 0x661118 },

		{ 0x011c, 0x66111c },

		{ 0x0130, 0x661130 },

		{ 0x0134, 0x661134 },

		{ 0x0138, 0x661138 },

		{ 0x013c, 0x66113c },

		{ 0x0140, 0x661140 },

		{ 0x0144, 0x661144 },

		{ 0x0148, 0x661148 },

		{ 0x014c, 0x66114c },

		{ 0x0150, 0x661150 },

		{ 0x0154, 0x661154 },

		{ 0x0158, 0x661158 },

		{ 0x015c, 0x66115c },

		{ 0x0160, 0x661160 },

		{ 0x0164, 0x661164 },

		{ 0x0168, 0x661168 },

		{ 0x016c, 0x66116c },

		{}

	}

};



static const struct nv50_disp_mthd_list

gf119_disp_base_mthd_image = {

	.mthd = 0x0020,

	.addr = 0x000020,

	.data = {

		{ 0x0400, 0x661400 },

		{ 0x0404, 0x661404 },

		{ 0x0408, 0x661408 },

		{ 0x040c, 0x66140c },

		{ 0x0410, 0x661410 },

		{}

	}

};



const struct nv50_disp_mthd_chan

gf119_disp_base_mthd_chan = {

	.name = "Base",

	.addr = 0x001000,

	.data = {

		{ "Global", 1, &gf119_disp_base_mthd_base },

		{  "Image", 2, &gf119_disp_base_mthd_image },

		{}

	}

};



struct nv50_disp_chan_impl

gf119_disp_base_ofuncs = {

	.base.ctor = nv50_disp_base_ctor,

	.base.dtor = nv50_disp_dmac_dtor,

	.base.init = gf119_disp_dmac_init,

	.base.fini = gf119_disp_dmac_fini,

	.base.ntfy = nv50_disp_chan_ntfy,

	.base.map  = nv50_disp_chan_map,

	.base.rd32 = nv50_disp_chan_rd32,

	.base.wr32 = nv50_disp_chan_wr32,

	.chid = 1,

	.attach = gf119_disp_dmac_object_attach,

	.detach = gf119_disp_dmac_object_detach,

};

drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c

0 → 100644
+127 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2012 Red Hat Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Ben Skeggs

 */

#include "dmacnv50.h"



#include <core/client.h>



#include <nvif/class.h>

#include <nvif/unpack.h>



static const struct nv50_disp_mthd_list

nv50_disp_base_mthd_base = {

	.mthd = 0x0000,

	.addr = 0x000000,

	.data = {

		{ 0x0080, 0x000000 },

		{ 0x0084, 0x0008c4 },

		{ 0x0088, 0x0008d0 },

		{ 0x008c, 0x0008dc },

		{ 0x0090, 0x0008e4 },

		{ 0x0094, 0x610884 },

		{ 0x00a0, 0x6108a0 },

		{ 0x00a4, 0x610878 },

		{ 0x00c0, 0x61086c },

		{ 0x00e0, 0x610858 },

		{ 0x00e4, 0x610860 },

		{ 0x00e8, 0x6108ac },

		{ 0x00ec, 0x6108b4 },

		{ 0x0100, 0x610894 },

		{ 0x0110, 0x6108bc },

		{ 0x0114, 0x61088c },

		{}

	}

};



const struct nv50_disp_mthd_list

nv50_disp_base_mthd_image = {

	.mthd = 0x0400,

	.addr = 0x000000,

	.data = {

		{ 0x0800, 0x6108f0 },

		{ 0x0804, 0x6108fc },

		{ 0x0808, 0x61090c },

		{ 0x080c, 0x610914 },

		{ 0x0810, 0x610904 },

		{}

	}

};



const struct nv50_disp_mthd_chan

nv50_disp_base_mthd_chan = {

	.name = "Base",

	.addr = 0x000540,

	.data = {

		{ "Global", 1, &nv50_disp_base_mthd_base },

		{  "Image", 2, &nv50_disp_base_mthd_image },

		{}

	}

};



int

nv50_disp_base_ctor(struct nvkm_object *parent,

		    struct nvkm_object *engine,

		    struct nvkm_oclass *oclass, void *data, u32 size,

		    struct nvkm_object **pobject)

{

	union {

		struct nv50_disp_base_channel_dma_v0 v0;

	} *args = data;

	struct nv50_disp *disp = (void *)engine;

	struct nv50_disp_dmac *dmac;

	int ret;



	nvif_ioctl(parent, "create disp base channel dma size %d\n", size);

	if (nvif_unpack(args->v0, 0, 0, false)) {

		nvif_ioctl(parent, "create disp base channel dma vers %d "

				   "pushbuf %016llx head %d\n",

			   args->v0.version, args->v0.pushbuf, args->v0.head);

		if (args->v0.head > disp->head.nr)

			return -EINVAL;

	} else

		return ret;



	ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf,

				     args->v0.head, sizeof(*dmac),

				     (void **)&dmac);

	*pobject = nv_object(dmac);

	if (ret)

		return ret;



	return 0;

}



struct nv50_disp_chan_impl

nv50_disp_base_ofuncs = {

	.base.ctor = nv50_disp_base_ctor,

	.base.dtor = nv50_disp_dmac_dtor,

	.base.init = nv50_disp_dmac_init,

	.base.fini = nv50_disp_dmac_fini,

	.base.ntfy = nv50_disp_chan_ntfy,

	.base.map  = nv50_disp_chan_map,

	.base.rd32 = nv50_disp_chan_rd32,

	.base.wr32 = nv50_disp_chan_wr32,

	.chid = 1,

	.attach = nv50_disp_dmac_object_attach,

	.detach = nv50_disp_dmac_object_detach,

};