Commit 298b0c8b authored by Kuninori Morimoto's avatar Kuninori Morimoto Committed by Geert Uytterhoeven
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arm64: dts: renesas: r8a77961: Add VSP device nodes 



This patch adds VSP device nodes for R-Car M3-W+ (r8a77961) SoC.
This patch was tested on R-Car M3-W+ Salvator-XS board.

Signed-off-by: default avatarKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: default avatarKieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/87lfhm70s6.wl-kuninori.morimoto.gx@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 9ab84704

arch/arm64/boot/dts/renesas/r8a77961.dtsi

+55 −0
Original line number Diff line number Diff line
@@ -1984,6 +1984,61 @@ fcpvd2: fcp@fea37000 { 
			iommus = <&ipmmu_vi0 10>;

		};



		vspb: vsp@fe960000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe960000 0 0x8000>;

			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 626>;

			power-domains = <&sysc R8A77961_PD_A3VC>;

			resets = <&cpg 626>;



			renesas,fcp = <&fcpvb0>;

		};



		vspd0: vsp@fea20000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea20000 0 0x5000>;

			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 623>;

			power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;

			resets = <&cpg 623>;



			renesas,fcp = <&fcpvd0>;

		};



		vspd1: vsp@fea28000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea28000 0 0x5000>;

			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 622>;

			power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;

			resets = <&cpg 622>;



			renesas,fcp = <&fcpvd1>;

		};



		vspd2: vsp@fea30000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea30000 0 0x5000>;

			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 621>;

			power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;

			resets = <&cpg 621>;



			renesas,fcp = <&fcpvd2>;

		};



		vspi0: vsp@fe9a0000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe9a0000 0 0x8000>;

			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 631>;

			power-domains = <&sysc R8A77961_PD_A3VC>;

			resets = <&cpg 631>;



			renesas,fcp = <&fcpvi0>;

		};



		csi20: csi2@fea80000 {

			reg = <0 0xfea80000 0 0x10000>;

			/* placeholder */