Commit 2785cc00 authored by Sascha Hauer's avatar Sascha Hauer Committed by Chanwoo Choi
Browse files

PM / devfreq: rockchip-dfi: give variable a better name 

struct dmc_count_channel::total counts the clock cycles of the DDR
controller. Rename it accordingly to give the reader a better idea
what this is about. While at it, at some documentation to struct
dmc_count_channel.

Link: https://lore.kernel.org/all/20231018061714.3553817-16-s.hauer@pengutronix.de/


Reviewed-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
parent d724f4a4

drivers/devfreq/event/rockchip-dfi.c

+12 −7
Original line number Diff line number Diff line
@@ -46,9 +46,14 @@ 
#define DDRMON_CH1_COUNT_NUM		0x3c

#define DDRMON_CH1_DFI_ACCESS_NUM	0x40



/**

 * struct dmc_count_channel - structure to hold counter values from the DDR controller

 * @access:       Number of read and write accesses

 * @clock_cycles: DDR clock cycles

 */

struct dmc_count_channel {

	u32 access;

	u32 total;

	u32 clock_cycles;

};



struct dmc_count {
@@ -151,7 +156,7 @@ static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_coun 
			continue;

		count->c[i].access = readl_relaxed(dfi_regs +

				DDRMON_CH0_DFI_ACCESS_NUM + i * 20);

		count->c[i].total = readl_relaxed(dfi_regs +

		count->c[i].clock_cycles = readl_relaxed(dfi_regs +

				DDRMON_CH0_COUNT_NUM + i * 20);

	}

}
@@ -183,29 +188,29 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev, 
	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);

	struct dmc_count count;

	struct dmc_count *last = &dfi->last_event_count;

	u32 access = 0, total = 0;

	u32 access = 0, clock_cycles = 0;

	int i;



	rockchip_dfi_read_counters(dfi, &count);



	/* We can only report one channel, so find the busiest one */

	for (i = 0; i < dfi->max_channels; i++) {

		u32 a, t;

		u32 a, c;



		if (!(dfi->channel_mask & BIT(i)))

			continue;



		a = count.c[i].access - last->c[i].access;

		t = count.c[i].total - last->c[i].total;

		c = count.c[i].clock_cycles - last->c[i].clock_cycles;



		if (a > access) {

			access = a;

			total = t;

			clock_cycles = c;

		}

	}



	edata->load_count = access * 4;

	edata->total_count = total;

	edata->total_count = clock_cycles;



	dfi->last_event_count = count;