Unverified Commit 21ed2f61 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'sti-dt-for-v5.18-round1' of... 

Merge tag 'sti-dt-for-v5.18-round1' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti

 into arm/dt

STi DT update:
- various DT fixes to avoid warnings when build with W=1
- DT clean-up

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 6f50ebf2 44d5061f

arch/arm/boot/dts/stih407-clock.dtsi

+46 −55
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ clocks { 
		 */

		clockgen-a9@92b0000 {

			compatible = "st,clkgen-c32";

			reg = <0x92b0000 0xffff>;

			reg = <0x92b0000 0x10000>;



			clockgen_a9_pll: clockgen-a9-pll {

				#clock-cells = <1>;
@@ -37,22 +37,16 @@ clockgen_a9_pll: clockgen-a9-pll { 


				clocks = <&clk_sysin>;

			};

		};



		/*

		 * ARM CPU related clocks.

		 */

		clk_m_a9: clk-m-a9@92b0000 {

			clk_m_a9: clk-m-a9 {

				#clock-cells = <0>;

				compatible = "st,stih407-clkgen-a9-mux";

			reg = <0x92b0000 0x10000>;



				clocks = <&clockgen_a9_pll 0>,

					 <&clockgen_a9_pll 0>,

					 <&clk_s_c0_flexgen 13>,

					 <&clk_m_a9_ext2f_div2>;





				/*

				 * ARM Peripheral clock for timers

				 */
@@ -65,6 +59,7 @@ arm_periph_clk: clk-m-a9-periphs { 
					clock-mult = <1>;

				};

			};

		};



		clockgen-a@90ff000 {

			compatible = "st,clkgen-c32";
@@ -87,14 +82,6 @@ clk_s_a0_flexgen: clk-s-a0-flexgen { 
			};

		};



		clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {

			#clock-cells = <1>;

			compatible = "st,quadfs-pll";

			reg = <0x9103000 0x1000>;



			clocks = <&clk_sysin>;

		};



		clk_s_c0: clockgen-c@9103000 {

			compatible = "st,clkgen-c32";

			reg = <0x9103000 0x1000>;
@@ -113,6 +100,13 @@ clk_s_c0_pll1: clk-s-c0-pll1 { 
				clocks = <&clk_sysin>;

			};



			clk_s_c0_quadfs: clk-s-c0-quadfs {

				#clock-cells = <1>;

				compatible = "st,quadfs-pll";



				clocks = <&clk_sysin>;

			};



			clk_s_c0_flexgen: clk-s-c0-flexgen {

				#clock-cells = <1>;

				compatible = "st,flexgen", "st,flexgen-stih407-c0";
@@ -142,18 +136,17 @@ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { 
			};

		};



		clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {

		clockgen-d0@9104000 {

			compatible = "st,clkgen-c32";

			reg = <0x9104000 0x1000>;



			clk_s_d0_quadfs: clk-s-d0-quadfs {

				#clock-cells = <1>;

				compatible = "st,quadfs-d0";

			reg = <0x9104000 0x1000>;



				clocks = <&clk_sysin>;

			};



		clockgen-d0@9104000 {

			compatible = "st,clkgen-c32";

			reg = <0x9104000 0x1000>;



			clk_s_d0_flexgen: clk-s-d0-flexgen {

				#clock-cells = <1>;

				compatible = "st,flexgen", "st,flexgen-stih407-d0";
@@ -166,18 +159,17 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { 
			};

		};



		clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {

		clockgen-d2@9106000 {

			compatible = "st,clkgen-c32";

			reg = <0x9106000 0x1000>;



			clk_s_d2_quadfs: clk-s-d2-quadfs {

				#clock-cells = <1>;

				compatible = "st,quadfs-d2";

			reg = <0x9106000 0x1000>;



				clocks = <&clk_sysin>;

			};



		clockgen-d2@9106000 {

			compatible = "st,clkgen-c32";

			reg = <0x9106000 0x1000>;



			clk_s_d2_flexgen: clk-s-d2-flexgen {

				#clock-cells = <1>;

				compatible = "st,flexgen", "st,flexgen-stih407-d2";
@@ -192,18 +184,17 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { 
			};

		};



		clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {

		clockgen-d3@9107000 {

			compatible = "st,clkgen-c32";

			reg = <0x9107000 0x1000>;



			clk_s_d3_quadfs: clk-s-d3-quadfs {

				#clock-cells = <1>;

				compatible = "st,quadfs-d3";

			reg = <0x9107000 0x1000>;



				clocks = <&clk_sysin>;

			};



		clockgen-d3@9107000 {

			compatible = "st,clkgen-c32";

			reg = <0x9107000 0x1000>;



			clk_s_d3_flexgen: clk-s-d3-flexgen {

				#clock-cells = <1>;

				compatible = "st,flexgen", "st,flexgen-stih407-d3";

arch/arm/boot/dts/stih407-family.dtsi

+126 −136
Original line number Diff line number Diff line
@@ -115,38 +115,141 @@ pwm_regulator: pwm-regulator { 
		status = "okay";

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;

		interrupt-parent = <&intc>;

		ranges;

		compatible = "simple-bus";



		restart: restart-controller@0 {

	restart: restart-controller {

		compatible = "st,stih407-restart";

			reg = <0 0>;

		st,syscfg = <&syscfg_sbc_reg>;

		status = "okay";

	};



		powerdown: powerdown-controller@0 {

	powerdown: powerdown-controller {

		compatible = "st,stih407-powerdown";

			reg = <0 0>;

		#reset-cells = <1>;

	};



		softreset: softreset-controller@0 {

	softreset: softreset-controller {

		compatible = "st,stih407-softreset";

			reg = <0 0>;

		#reset-cells = <1>;

	};



		picophyreset: picophyreset-controller@0 {

	picophyreset: picophyreset-controller {

		compatible = "st,stih407-picophyreset";

			reg = <0 0>;

		#reset-cells = <1>;

	};



	irq-syscfg {

		compatible    = "st,stih407-irq-syscfg";

		st,syscfg     = <&syscfg_core>;

		st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,

				<ST_IRQ_SYSCFG_PMU_1>;

		st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,

				<ST_IRQ_SYSCFG_DISABLED>;

	};



	usb2_picophy0: phy1 {

		compatible = "st,stih407-usb2-phy";

		#phy-cells = <0>;

		st,syscfg = <&syscfg_core 0x100 0xf4>;

		resets = <&softreset STIH407_PICOPHY_SOFTRESET>,

			 <&picophyreset STIH407_PICOPHY2_RESET>;

		reset-names = "global", "port";

	};



	miphy28lp_phy: miphy28lp {

		compatible = "st,miphy28lp-phy";

		st,syscfg = <&syscfg_core>;

		#address-cells	= <1>;

		#size-cells	= <1>;

		ranges;



		phy_port0: port@9b22000 {

			reg = <0x9b22000 0xff>,

			      <0x9b09000 0xff>,

			      <0x9b04000 0xff>;

			reg-names = "sata-up",

				    "pcie-up",

				    "pipew";



			st,syscfg = <0x114 0x818 0xe0 0xec>;

			#phy-cells = <1>;



			reset-names = "miphy-sw-rst";

			resets = <&softreset STIH407_MIPHY0_SOFTRESET>;

		};



		phy_port1: port@9b2a000 {

			reg = <0x9b2a000 0xff>,

			      <0x9b19000 0xff>,

			      <0x9b14000 0xff>;

			reg-names = "sata-up",

				    "pcie-up",

				    "pipew";



			st,syscfg = <0x118 0x81c 0xe4 0xf0>;



			#phy-cells = <1>;



			reset-names = "miphy-sw-rst";

			resets = <&softreset STIH407_MIPHY1_SOFTRESET>;

		};



		phy_port2: port@8f95000 {

			reg = <0x8f95000 0xff>,

			      <0x8f90000 0xff>;

			reg-names = "pipew",

				    "usb3-up";



			st,syscfg = <0x11c 0x820>;



			#phy-cells = <1>;



			reset-names = "miphy-sw-rst";

			resets = <&softreset STIH407_MIPHY2_SOFTRESET>;

		};

	};



	st231_gp0: st231-gp0 {

		compatible	= "st,st231-rproc";

		memory-region	= <&gp0_reserved>;

		resets		= <&softreset STIH407_ST231_GP0_SOFTRESET>;

		reset-names	= "sw_reset";

		clocks		= <&clk_s_c0_flexgen CLK_ST231_GP_0>;

		clock-frequency	= <600000000>;

		st,syscfg	= <&syscfg_core 0x22c>;

		#mbox-cells = <1>;

		mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";

		mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;

	};



	st231_delta: st231-delta {

		compatible	= "st,st231-rproc";

		memory-region	= <&delta_reserved>;

		resets		= <&softreset STIH407_ST231_DMU_SOFTRESET>;

		reset-names	= "sw_reset";

		clocks		= <&clk_s_c0_flexgen CLK_ST231_DMU>;

		clock-frequency	= <600000000>;

		st,syscfg	= <&syscfg_core 0x224>;

		#mbox-cells = <1>;

		mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";

		mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;

	};



	delta0 {

		compatible = "st,st-delta";

		clock-names = "delta",

			      "delta-st231",

			      "delta-flash-promip";

		clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,

			 <&clk_s_c0_flexgen CLK_ST231_DMU>,

			 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;

		interrupt-parent = <&intc>;

		ranges;

		compatible = "simple-bus";



		syscfg_sbc: sbc-syscfg@9620000 {

			compatible = "st,stih407-sbc-syscfg", "syscon";

			reg = <0x9620000 0x1000>;
@@ -189,16 +292,6 @@ syscfg_lpm: lpm-syscfg@94b5100 { 
			reg = <0x94b5100 0x1000>;

		};



		irq-syscfg@0 {

			compatible    = "st,stih407-irq-syscfg";

			reg = <0 0>;

			st,syscfg     = <&syscfg_core>;

			st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,

					<ST_IRQ_SYSCFG_PMU_1>;

			st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,

					<ST_IRQ_SYSCFG_DISABLED>;

		};



		/* Display */

		vtg_main: sti-vtg-main@8d02800 {

			compatible = "st,vtg";
@@ -389,70 +482,6 @@ i2c@9541000 { 
			status = "disabled";

		};



		usb2_picophy0: phy1@0 {

			compatible = "st,stih407-usb2-phy";

			reg = <0 0>;

			#phy-cells = <0>;

			st,syscfg = <&syscfg_core 0x100 0xf4>;

			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,

				 <&picophyreset STIH407_PICOPHY2_RESET>;

			reset-names = "global", "port";

		};



		miphy28lp_phy: miphy28lp@0 {

			compatible = "st,miphy28lp-phy";

			st,syscfg = <&syscfg_core>;

			#address-cells	= <1>;

			#size-cells	= <1>;

			ranges;

			reg = <0 0>;



			phy_port0: port@9b22000 {

				reg = <0x9b22000 0xff>,

				      <0x9b09000 0xff>,

				      <0x9b04000 0xff>;

				reg-names = "sata-up",

					    "pcie-up",

					    "pipew";



				st,syscfg = <0x114 0x818 0xe0 0xec>;

				#phy-cells = <1>;



				reset-names = "miphy-sw-rst";

				resets = <&softreset STIH407_MIPHY0_SOFTRESET>;

			};



			phy_port1: port@9b2a000 {

				reg = <0x9b2a000 0xff>,

				      <0x9b19000 0xff>,

				      <0x9b14000 0xff>;

				reg-names = "sata-up",

					    "pcie-up",

					    "pipew";



				st,syscfg = <0x118 0x81c 0xe4 0xf0>;



				#phy-cells = <1>;



				reset-names = "miphy-sw-rst";

				resets = <&softreset STIH407_MIPHY1_SOFTRESET>;

			};



			phy_port2: port@8f95000 {

				reg = <0x8f95000 0xff>,

				      <0x8f90000 0xff>;

				reg-names = "pipew",

					    "usb3-up";



				st,syscfg = <0x11c 0x820>;



				#phy-cells = <1>;



				reset-names = "miphy-sw-rst";

				resets = <&softreset STIH407_MIPHY2_SOFTRESET>;

			};

		};



		spi@9840000 {

			compatible = "st,comms-ssc4-spi";

			reg = <0x9840000 0x110>;
@@ -815,34 +844,6 @@ mailbox3: mailbox@8f03000 { 
			status		= "okay";

		};



		st231_gp0: st231-gp0@0 {

			compatible	= "st,st231-rproc";

			reg		= <0 0>;

			memory-region	= <&gp0_reserved>;

			resets		= <&softreset STIH407_ST231_GP0_SOFTRESET>;

			reset-names	= "sw_reset";

			clocks		= <&clk_s_c0_flexgen CLK_ST231_GP_0>;

			clock-frequency	= <600000000>;

			st,syscfg	= <&syscfg_core 0x22c>;

			#mbox-cells = <1>;

			mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";

			mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;

		};



		st231_delta: st231-delta@0 {

			compatible	= "st,st231-rproc";

			reg		= <0 0>;

			memory-region	= <&delta_reserved>;

			resets		= <&softreset STIH407_ST231_DMU_SOFTRESET>;

			reset-names	= "sw_reset";

			clocks		= <&clk_s_c0_flexgen CLK_ST231_DMU>;

			clock-frequency	= <600000000>;

			st,syscfg	= <&syscfg_core 0x224>;

			#mbox-cells = <1>;

			mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";

			mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;

		};



		/* fdma audio */

		fdma0: dma-controller@8e20000 {

			compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
@@ -986,16 +987,5 @@ sti_uni_reader1: sti-uni-reader@8d84000 { 


			status = "disabled";

		};



		delta0@0 {

			compatible = "st,st-delta";

			reg = <0 0>;

			clock-names = "delta",

				      "delta-st231",

				      "delta-flash-promip";

			clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,

				 <&clk_s_c0_flexgen CLK_ST231_DMU>,

				 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;

		};

	};

};

arch/arm/boot/dts/stih410-b2120.dts

+8 −8
Original line number Diff line number Diff line
@@ -24,6 +24,14 @@ aliases { 
		ethernet0 = &ethernet0;

	};



	usb2_picophy1: phy2 {

		status = "okay";

	};



	usb2_picophy2: phy3 {

		status = "okay";

	};



	soc {



		mmc0: sdhci@9060000 {
@@ -33,14 +41,6 @@ mmc0: sdhci@9060000 { 
			sd-uhs-ddr50;

		};



		usb2_picophy1: phy2@0 {

			status = "okay";

		};



		usb2_picophy2: phy3@0 {

			status = "okay";

		};



		ohci0: usb@9a03c00 {

			status = "okay";

		};

arch/arm/boot/dts/stih410-b2260.dts

+15 −15
Original line number Diff line number Diff line
@@ -75,6 +75,21 @@ codec { 
		};

	};



	miphy28lp_phy: miphy28lp {



		phy_port1: port@9b2a000 {

			st,osc-force-ext;

		};

	};



	usb2_picophy1: phy2 {

		status = "okay";

	};



	usb2_picophy2: phy3 {

		status = "okay";

	};



	soc {

		/* Low speed expansion connector */

		uart0: serial@9830000 {
@@ -145,14 +160,6 @@ pwm1: pwm@9510000 { 
			status = "okay";

		};



		usb2_picophy1: phy2@0 {

			status = "okay";

		};



		usb2_picophy2: phy3@0 {

			status = "okay";

		};



		ohci0: usb@9a03c00 {

			status = "okay";

		};
@@ -196,13 +203,6 @@ hdmiddc: i2c@9541000 { 
			status = "okay";

		};



		miphy28lp_phy: miphy28lp@0 {



			phy_port1: port@9b2a000 {

				st,osc-force-ext;

			};

		};



		sata1: sata@9b28000 {

			status = "okay";

		};

arch/arm/boot/dts/stih410-clock.dtsi

+48 −52
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ clocks { 
		 */

		clockgen-a9@92b0000 {

			compatible = "st,clkgen-c32";

			reg = <0x92b0000 0xffff>;

			reg = <0x92b0000 0x10000>;



			clockgen_a9_pll: clockgen-a9-pll {

				#clock-cells = <1>;
@@ -40,20 +40,19 @@ clockgen_a9_pll: clockgen-a9-pll { 


				clocks = <&clk_sysin>;

			};

		};



			/*

			 * ARM CPU related clocks.

			 */

		clk_m_a9: clk-m-a9@92b0000 {

			clk_m_a9: clk-m-a9 {

				#clock-cells = <0>;

				compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";

			reg = <0x92b0000 0x10000>;



				clocks = <&clockgen_a9_pll 0>,

					 <&clockgen_a9_pll 0>,

					 <&clk_s_c0_flexgen 13>,

					 <&clk_m_a9_ext2f_div2>;



				/*

				 * ARM Peripheral clock for timers

				 */
@@ -65,6 +64,7 @@ arm_periph_clk: clk-m-a9-periphs { 
					clock-mult = <1>;

				};

			};

		};



		clockgen-a@90ff000 {

			compatible = "st,clkgen-c32";
@@ -87,14 +87,6 @@ clk_s_a0_flexgen: clk-s-a0-flexgen { 
			};

		};



		clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {

			#clock-cells = <1>;

			compatible = "st,quadfs-pll";

			reg = <0x9103000 0x1000>;



			clocks = <&clk_sysin>;

		};



		clk_s_c0: clockgen-c@9103000 {

			compatible = "st,clkgen-c32";

			reg = <0x9103000 0x1000>;
@@ -113,6 +105,13 @@ clk_s_c0_pll1: clk-s-c0-pll1 { 
				clocks = <&clk_sysin>;

			};



			clk_s_c0_quadfs: clk-s-c0-quadfs {

				#clock-cells = <1>;

				compatible = "st,quadfs-pll";



				clocks = <&clk_sysin>;

			};



			clk_s_c0_flexgen: clk-s-c0-flexgen {

				#clock-cells = <1>;

				compatible = "st,flexgen", "st,flexgen-stih410-c0";
@@ -142,18 +141,17 @@ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { 
			};

		};



		clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {

		clockgen-d0@9104000 {

			compatible = "st,clkgen-c32";

			reg = <0x9104000 0x1000>;



			clk_s_d0_quadfs: clk-s-d0-quadfs {

				#clock-cells = <1>;

				compatible = "st,quadfs-d0";

			reg = <0x9104000 0x1000>;



				clocks = <&clk_sysin>;

			};



		clockgen-d0@9104000 {

			compatible = "st,clkgen-c32";

			reg = <0x9104000 0x1000>;



			clk_s_d0_flexgen: clk-s-d0-flexgen {

				#clock-cells = <1>;

				compatible = "st,flexgen", "st,flexgen-stih410-d0";
@@ -166,18 +164,17 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { 
			};

		};



		clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {

		clockgen-d2@9106000 {

			compatible = "st,clkgen-c32";

			reg = <0x9106000 0x1000>;



			clk_s_d2_quadfs: clk-s-d2-quadfs {

				#clock-cells = <1>;

				compatible = "st,quadfs-d2";

			reg = <0x9106000 0x1000>;



				clocks = <&clk_sysin>;

			};



		clockgen-d2@9106000 {

			compatible = "st,clkgen-c32";

			reg = <0x9106000 0x1000>;



			clk_s_d2_flexgen: clk-s-d2-flexgen {

				#clock-cells = <1>;

				compatible = "st,flexgen", "st,flexgen-stih407-d2";
@@ -192,18 +189,17 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { 
			};

		};



		clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {

		clockgen-d3@9107000 {

			compatible = "st,clkgen-c32";

			reg = <0x9107000 0x1000>;



			clk_s_d3_quadfs: clk-s-d3-quadfs {

				#clock-cells = <1>;

				compatible = "st,quadfs-d3";

			reg = <0x9107000 0x1000>;



				clocks = <&clk_sysin>;

			};



		clockgen-d3@9107000 {

			compatible = "st,clkgen-c32";

			reg = <0x9107000 0x1000>;



			clk_s_d3_flexgen: clk-s-d3-flexgen {

				#clock-cells = <1>;

				compatible = "st,flexgen", "st,flexgen-stih407-d3";