Commit 2166d9fb authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: update audio wall clock programming 



[why]
for audio on real TV issue.

[how]
-add wall clock programming for DPREF based when
Pixel clock is done by DP DTO.

Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Reviewed-by: default avatarChris Park <Chris.Park@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 92bfc4a1

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

+3 −1
Original line number Diff line number Diff line
@@ -140,6 +140,8 @@ static void check_audio_bandwidth_hdmi( 
	bool limit_freq_to_88_2_khz = false;

	bool limit_freq_to_96_khz = false;

	bool limit_freq_to_174_4_khz = false;

	if (!crtc_info)

		return;



	/* For two channels supported return whatever sink support,unmodified*/

	if (channel_count > 2) {
@@ -784,7 +786,7 @@ void dce_aud_wall_dto_setup( 


	struct azalia_clock_info clock_info = { 0 };



	if (dc_is_hdmi_signal(signal)) {

	if (dc_is_hdmi_tmds_signal(signal)) {

		uint32_t src_sel;



		/*DTO0 Programming goal:

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+1 −3
Original line number Diff line number Diff line
@@ -1148,7 +1148,7 @@ static void build_audio_output( 
			pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;



/*for HDMI, audio ACR is with deep color ratio factor*/

	if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&

	if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&

		audio_output->crtc_info.requested_pixel_clock_100Hz ==

				(stream->timing.pix_clk_100hz)) {

		if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
@@ -1963,10 +1963,8 @@ static void dce110_setup_audio_dto( 


		if (pipe_ctx->top_pipe)

			continue;



		if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)

			continue;



		if (pipe_ctx->stream_res.audio != NULL) {

			struct audio_output audio_output;