Commit 1f5e4c15 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-fixes' into clk-next 

* clk-fixes:
  clk: x86: Do not gate clocks enabled by the firmware
  clk: gemini: Fix reset regression
parents 4aafe9c6 d31fd43c

drivers/clk/clk-gemini.c

+14 −0
Original line number Diff line number Diff line
@@ -237,6 +237,18 @@ static int gemini_reset(struct reset_controller_dev *rcdev, 
			    BIT(GEMINI_RESET_CPU1) | BIT(id));

}



static int gemini_reset_assert(struct reset_controller_dev *rcdev,

			       unsigned long id)

{

	return 0;

}



static int gemini_reset_deassert(struct reset_controller_dev *rcdev,

				 unsigned long id)

{

	return 0;

}



static int gemini_reset_status(struct reset_controller_dev *rcdev,

			     unsigned long id)

{
@@ -253,6 +265,8 @@ static int gemini_reset_status(struct reset_controller_dev *rcdev, 


static const struct reset_control_ops gemini_reset_ops = {

	.reset = gemini_reset,

	.assert = gemini_reset_assert,

	.deassert = gemini_reset_deassert,

	.status = gemini_reset_status,

};

drivers/clk/x86/clk-pmc-atom.c

+7 −0
Original line number Diff line number Diff line
@@ -186,6 +186,13 @@ static struct clk_plt *plt_clk_register(struct platform_device *pdev, int id, 
	pclk->reg = base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE;

	spin_lock_init(&pclk->lock);



	/*

	 * If the clock was already enabled by the firmware mark it as critical

	 * to avoid it being gated by the clock framework if no driver owns it.

	 */

	if (plt_clk_is_enabled(&pclk->hw))

		init.flags |= CLK_IS_CRITICAL;



	ret = devm_clk_hw_register(&pdev->dev, &pclk->hw);

	if (ret) {

		pclk = ERR_PTR(ret);