Commit 1f02c97b authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
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drm/amd/amdgpu: Add GFX9.1 PWR_MISC_CNTL_STATUS register to headers 



The registers are needed for umr and not in the headers.  I left them
in the gfx_v9_0.c since it includes 9.0 and 9.4 headers and including
9.1 headers would result in a lot of duplicate registers clashing.

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 18485be9

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

+2 −0
Original line number Diff line number Diff line
@@ -159,6 +159,8 @@ 
#define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX                                                              0

#define mmCP_DE_DE_COUNT                                                                               0x00c4

#define mmCP_DE_DE_COUNT_BASE_IDX                                                                      0

#define mmPWR_MISC_CNTL_STATUS                                                                         0x0183

#define mmPWR_MISC_CNTL_STATUS_BASE_IDX                                                                0

#define mmCP_STALLED_STAT3                                                                             0x019c

#define mmCP_STALLED_STAT3_BASE_IDX                                                                    0

#define mmCP_STALLED_STAT1                                                                             0x019d

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

+5 −0
Original line number Diff line number Diff line
@@ -801,6 +801,11 @@ 
//CP_DE_DE_COUNT

#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT                                                              0x0

#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL

//PWR_MISC_CNTL_STATUS

#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT                                                      0x0

#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT                                                        0x1

#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK                                                        0x00000001L

#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK                                                          0x00000006L

//CP_STALLED_STAT3

#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT                                                     0x0

#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT                                        0x1