Commit 1edf5ae1 authored by Zhan Liu's avatar Zhan Liu Committed by Alex Deucher
Browse files

drm/amd/display: enable seamless boot for DCN301 



[Why]
DCN301 is capable of running seamless boot
if keep_stolen_vga_memory is not set.

[How]
Add a helper to check whether an ASIC can support
seamless boot and set it based on base driver flags.

Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarZhan Liu <Zhan.Liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 85fb8bb9

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+27 −0
Original line number Diff line number Diff line
@@ -1454,6 +1454,12 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) 


	init_data.flags.power_down_display_on_boot = true;



	if (check_seamless_boot_capability(adev)) {

		init_data.flags.power_down_display_on_boot = false;

		init_data.flags.allow_seamless_boot_optimization = true;

		DRM_INFO("Seamless boot condition check passed\n");

	}



	INIT_LIST_HEAD(&adev->dm.da_list);

	/* Display Core create. */

	adev->dm.dc = dc_create(&init_data);
@@ -11616,3 +11622,24 @@ int amdgpu_dm_process_dmub_aux_transfer_sync(bool is_cmd_aux, struct dc_context 
			ctx, DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS,

			(uint32_t *)operation_result);

}



/*

 * Check whether seamless boot is supported.

 *

 * So far we only support seamless boot on CHIP_VANGOGH.

 * If everything goes well, we may consider expanding

 * seamless boot to other ASICs.

 */

bool check_seamless_boot_capability(struct amdgpu_device *adev)

{

	switch (adev->asic_type) {

	case CHIP_VANGOGH:

		if (!adev->mman.keep_stolen_vga_memory)

			return true;

		break;

	default:

		break;

	}



	return false;

}

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

+3 −0
Original line number Diff line number Diff line
@@ -731,4 +731,7 @@ extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 
int amdgpu_dm_process_dmub_aux_transfer_sync(bool is_cmd_aux,

					struct dc_context *ctx, unsigned int link_index,

					void *payload, void *operation_result);



bool check_seamless_boot_capability(struct amdgpu_device *adev);



#endif /* __AMDGPU_DM_H__ */

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+0 −1
Original line number Diff line number Diff line
@@ -2078,7 +2078,6 @@ static void mark_seamless_boot_stream( 
{

	struct dc_bios *dcb = dc->ctx->dc_bios;



	/* TODO: Check Linux */

	if (dc->config.allow_seamless_boot_optimization &&

			!dcb->funcs->is_accelerated_mode(dcb)) {

		if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -686,7 +686,7 @@ static const struct dc_debug_options debug_defaults_drv = { 
	.disable_clock_gate = true,

	.disable_pplib_clock_request = true,

	.disable_pplib_wm_range = true,

	.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,

	.pipe_split_policy = MPC_SPLIT_AVOID,

	.force_single_disp_pipe_split = false,

	.disable_dcc = DCC_ENABLE,

	.vsr_support = true,