drm/amdgpu/gfx10: add updated register offsets for VGH

#define mmSPI_CONFIG_CNTL_1_Vangogh		 0x2441

#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX	 1

#define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261

#define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1

#define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f

#define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1

#define mmVGT_TF_RING_SIZE_Vangogh               0x224e

#define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1

#define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241

#define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1

#define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250

#define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1

#define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240

#define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1

#define mmSPI_CONFIG_CNTL_Vangogh                0x2440

#define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1

#define mmCP_HYP_PFP_UCODE_ADDR			0x5814

#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX	1