Commit 1de16e38 authored by Sergio Paracuellos's avatar Sergio Paracuellos Committed by Greg Kroah-Hartman
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staging: mt7621-pci: remove 'RALINK_PCI_IMBASEBAR0_ADDR' register 



Register 'RALINK_PCI_IMBASEBAR0_ADDR' contains internal memory
base address for BAR0. We don't really need to write anything
there at all since its initial value contains always a desired
valid value. Hence remove register definition and related code.

Signed-off-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20201123093637.8300-8-sergio.paracuellos@gmail.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 108b2f2a

drivers/staging/mt7621-pci/pci-mt7621.c

+0 −4
Original line number Diff line number Diff line
@@ -68,7 +68,6 @@ 
#define MT7621_NEXT_PORT		0x1000



#define RALINK_PCI_BAR0SETUP_ADDR	0x0010

#define RALINK_PCI_IMBASEBAR0_ADDR	0x0018

#define RALINK_PCI_ID			0x0030

#define RALINK_PCI_CLASS		0x0034

#define RALINK_PCI_SUBID		0x0038
@@ -83,7 +82,6 @@ 
#define PCIE_PORT_CLK_EN(x)		BIT(24 + (x))

#define PCIE_PORT_LINKUP		BIT(0)



#define MEMORY_BASE			0x0

#define PERST_MODE_MASK			GENMASK(11, 10)

#define PERST_MODE_GPIO			BIT(10)

#define PERST_DELAY_MS			100
@@ -543,8 +541,6 @@ static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port) 
	/* map 2G DDR region */

	pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,

		   offset + RALINK_PCI_BAR0SETUP_ADDR);

	pcie_write(pcie, MEMORY_BASE,

		   offset + RALINK_PCI_IMBASEBAR0_ADDR);



	/* configure class code and revision ID */

	pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,