Commit 1dc3e50e authored by Sai Prakash Ranjan's avatar Sai Prakash Ranjan Committed by Bjorn Andersson
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arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node 



Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on SM8450
SoC.

Signed-off-by: default avatarSai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: default avatarVinod Koul <vkoul@kernel.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/7995d003b77d5e066658af5b2cfa22ccb40b6cf7.1643355594.git.quic_saipraka@quicinc.com
parent 01b8c4af

arch/arm64/boot/dts/qcom/sm8450.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -1353,6 +1353,13 @@ gem_noc: interconnect@19100000 { 
			qcom,bcm-voters = <&apps_bcm_voter>;

		};



		system-cache-controller@19200000 {

			compatible = "qcom,sm8450-llcc";

			reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;

			reg-names = "llcc_base", "llcc_broadcast_base";

			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;

		};



		ufs_mem_hc: ufshc@1d84000 {

			compatible = "qcom,sm8450-ufshc", "qcom,ufshc",

				     "jedec,ufs-2.0";