Commit 1da7d4a8 authored by Rohit Khaire's avatar Rohit Khaire Committed by Alex Deucher
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drm/amdgpu: Write blocked CP registers using RLC on VF 



This change programs CP_ME_CNTL and RLC_CSIB_* through RLC

Signed-off-by: default avatarRohit Khaire <Rohit.Khaire@amd.com>
Reviewed-by: default avatarMonk Liu <monk.liu@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1d21a846

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+4 −4
Original line number Diff line number Diff line
@@ -1787,11 +1787,11 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 
	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);



	/* csib */

	WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,

	WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,

		     adev->gfx.rlc.clear_state_gpu_addr >> 32);

	WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,

	WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,

		     adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);

	WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);

	WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);



	return 0;

}
@@ -2399,7 +2399,7 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 
		for (i = 0; i < adev->gfx.num_gfx_rings; i++)

			adev->gfx.gfx_ring[i].sched.ready = false;

	}

	WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);

	WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);



	for (i = 0; i < adev->usec_timeout; i++) {

		if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)