Commit 1beb5512 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Lorenzo Pieralisi
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PCI: keystone: Cleanup interrupt related macros 



No functional change. Change both MSI interrupt and legacy interrupt
related macros to take an additional argument in order to return the
correct register offset.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
parent 9e98c678

drivers/pci/controller/dwc/pci-keystone.c

+13 −13
Original line number Diff line number Diff line
@@ -52,17 +52,17 @@ 


/* IRQ register defines */

#define IRQ_EOI				0x050

#define IRQ_STATUS			0x184

#define IRQ_ENABLE_SET			0x188

#define IRQ_ENABLE_CLR			0x18c



#define MSI_IRQ				0x054

#define MSI0_IRQ_STATUS			0x104

#define MSI0_IRQ_ENABLE_SET		0x108

#define MSI0_IRQ_ENABLE_CLR		0x10c

#define IRQ_STATUS			0x184

#define MSI_IRQ_STATUS(n)		(0x104 + ((n) << 4))

#define MSI_IRQ_ENABLE_SET(n)		(0x108 + ((n) << 4))

#define MSI_IRQ_ENABLE_CLR(n)		(0x10c + ((n) << 4))

#define MSI_IRQ_OFFSET			4



#define IRQ_STATUS(n)			(0x184 + ((n) << 4))

#define IRQ_ENABLE_SET(n)		(0x188 + ((n) << 4))

#define INTx_EN				BIT(0)



#define ERR_IRQ_STATUS			0x1c4

#define ERR_IRQ_ENABLE_SET		0x1c8

#define ERR_AER				BIT(5)	/* ECRC error */
@@ -142,7 +142,7 @@ static void ks_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset) 
	u32 pending, vector;

	int src, virq;



	pending = ks_pcie_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4));

	pending = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset));



	/*

	 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
@@ -169,7 +169,7 @@ static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp) 
	ks_pcie = to_keystone_pcie(pci);

	update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);



	ks_pcie_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4),

	ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset),

			   BIT(bit_pos));

	ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);

}
@@ -181,7 +181,7 @@ static void ks_pcie_msi_set_irq(struct pcie_port *pp, int irq) 
	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);



	update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);

	ks_pcie_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4),

	ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset),

			   BIT(bit_pos));

}
@@ -192,7 +192,7 @@ static void ks_pcie_msi_clear_irq(struct pcie_port *pp, int irq) 
	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);



	update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);

	ks_pcie_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4),

	ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset),

			   BIT(bit_pos));

}
@@ -206,7 +206,7 @@ static void ks_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie) 
	int i;



	for (i = 0; i < PCI_NUM_INTX; i++)

		ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1);

		ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), 0x1);

}



static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie,
@@ -217,7 +217,7 @@ static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, 
	u32 pending;

	int virq;



	pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS + (offset << 4));

	pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset));



	if (BIT(0) & pending) {

		virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);