Commit 1be6b46f authored by Clint Taylor's avatar Clint Taylor Committed by Matt Roper
Browse files

drm/i915/dg2: add Wa_14014947963 



BSPEC: 46123
v2: Address review feedback [MattR]
v3: move register definition to gt_regs [MattR]
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarClint Taylor <clinton.a.taylor@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220211052333.12306-1-clinton.a.taylor@intel.com
parent 8fbf2893

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+3 −0
Original line number Diff line number Diff line
@@ -465,6 +465,9 @@ 
#define   GEN9_PGCTL_SSB_EU210_ACK		(1 << 12)

#define   GEN9_PGCTL_SSB_EU311_ACK		(1 << 14)



#define VF_PREEMPTION				_MMIO(0x83a4)

#define   PREEMPTION_VERTEX_COUNT		REG_GENMASK(15, 0)



#define GEN8_RC6_CTX_INFO			_MMIO(0x8504)



#define GEN12_SQCM				_MMIO(0x8724)

drivers/gpu/drm/i915/gt/intel_workarounds.c

+5 −0
Original line number Diff line number Diff line
@@ -683,6 +683,11 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 
	/* Wa_16013271637:dg2 */

	wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1,

		     MSC_MSAA_REODER_BUF_BYPASS_DISABLE);



	/* Wa_14014947963:dg2 */

	if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) ||

		IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))

		wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000);

}



static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,