Commit 1a4f20ca authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

Merge branch 'for-v5.20/exynos7885-emmc-clk' into next/dt64

parents 5c4a99cf ced37411

Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml

+27 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ properties: 
    enum:

      - samsung,exynos7885-cmu-top

      - samsung,exynos7885-cmu-core

      - samsung,exynos7885-cmu-fsys

      - samsung,exynos7885-cmu-peri



  clocks:
@@ -88,6 +89,32 @@ allOf: 
            - const: dout_core_cci

            - const: dout_core_g3d



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos7885-cmu-fsys



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_FSYS bus clock (from CMU_TOP)

            - description: MMC_CARD clock (from CMU_TOP)

            - description: MMC_EMBD clock (from CMU_TOP)

            - description: MMC_SDIO clock (from CMU_TOP)

            - description: USB30DRD clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_fsys_bus

            - const: dout_fsys_mmc_card

            - const: dout_fsys_mmc_embd

            - const: dout_fsys_mmc_sdio

            - const: dout_fsys_usb30drd



  - if:

      properties:

        compatible:

arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts

+20 −0
Original line number Diff line number Diff line
@@ -60,6 +60,26 @@ power-key { 
	};

};



&mmc_0 {

	status = "okay";

	mmc-hs200-1_8v;

	mmc-hs400-1_8v;

	cap-mmc-highspeed;

	non-removable;

	mmc-hs400-enhanced-strobe;

	card-detect-delay = <200>;

	clock-frequency = <800000000>;

	bus-width = <8>;

	samsung,dw-mshc-ciu-div = <3>;

	samsung,dw-mshc-sdr-timing = <0 4>;

	samsung,dw-mshc-ddr-timing = <2 4>;

	samsung,dw-mshc-hs400-timing = <0 2>;



	pinctrl-names = "default";

	pinctrl-0 = <&sd0_clk_fast_slew_rate_3x &sd0_cmd &sd0_rdqs

		     &sd0_bus1 &sd0_bus4 &sd0_bus8>;

};



&oscclk {

	clock-frequency = <26000000>;

};

arch/arm64/boot/dts/exynos/exynos7885.dtsi

+32 −0
Original line number Diff line number Diff line
@@ -240,6 +240,25 @@ cmu_top: clock-controller@12060000 { 
			clock-names = "oscclk";

		};



		cmu_fsys: clock-controller@13400000 {

			compatible = "samsung,exynos7885-cmu-fsys";

			reg = <0x13400000 0x8000>;

			#clock-cells = <1>;



			clocks = <&oscclk>,

				 <&cmu_top CLK_DOUT_FSYS_BUS>,

				 <&cmu_top CLK_DOUT_FSYS_MMC_CARD>,

				 <&cmu_top CLK_DOUT_FSYS_MMC_EMBD>,

				 <&cmu_top CLK_DOUT_FSYS_MMC_SDIO>,

				 <&cmu_top CLK_DOUT_FSYS_USB30DRD>;

			clock-names = "oscclk",

				      "dout_fsys_bus",

				      "dout_fsys_mmc_card",

				      "dout_fsys_mmc_embd",

				      "dout_fsys_mmc_sdio",

				      "dout_fsys_usb30drd";

		};



		pinctrl_alive: pinctrl@11cb0000 {

			compatible = "samsung,exynos7885-pinctrl";

			reg = <0x11cb0000 0x1000>;
@@ -274,6 +293,19 @@ pmu_system_controller: system-controller@11c80000 { 
			reg = <0x11c80000 0x10000>;

		};



		mmc_0: mmc@13500000 {

			compatible = "samsung,exynos7-dw-mshc-smu";

			reg = <0x13500000 0x2000>;

			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>,

				 <&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>;

			clock-names = "biu", "ciu";

			fifo-depth = <0x40>;

			status = "disabled";

		};



		serial_0: serial@13800000 {

			compatible = "samsung,exynos5433-uart";

			reg = <0x13800000 0x100>;

include/dt-bindings/clock/exynos7885.h

+45 −9
Original line number Diff line number Diff line
@@ -54,7 +54,22 @@ 
#define CLK_GOUT_PERI_USI0		43

#define CLK_GOUT_PERI_USI1		44

#define CLK_GOUT_PERI_USI2		45

#define TOP_NR_CLK			46

#define CLK_MOUT_FSYS_BUS		46

#define CLK_MOUT_FSYS_MMC_CARD		47

#define CLK_MOUT_FSYS_MMC_EMBD		48

#define CLK_MOUT_FSYS_MMC_SDIO		49

#define CLK_MOUT_FSYS_USB30DRD		50

#define CLK_DOUT_FSYS_BUS		51

#define CLK_DOUT_FSYS_MMC_CARD		52

#define CLK_DOUT_FSYS_MMC_EMBD		53

#define CLK_DOUT_FSYS_MMC_SDIO		54

#define CLK_DOUT_FSYS_USB30DRD		55

#define CLK_GOUT_FSYS_BUS		56

#define CLK_GOUT_FSYS_MMC_CARD		57

#define CLK_GOUT_FSYS_MMC_EMBD		58

#define CLK_GOUT_FSYS_MMC_SDIO		59

#define CLK_GOUT_FSYS_USB30DRD		60

#define TOP_NR_CLK			61



/* CMU_CORE */

#define CLK_MOUT_CORE_BUS_USER			1
@@ -64,7 +79,14 @@ 
#define CLK_DOUT_CORE_BUSP			5

#define CLK_GOUT_CCI_ACLK			6

#define CLK_GOUT_GIC400_CLK			7

#define CORE_NR_CLK			8

#define CLK_GOUT_TREX_D_CORE_ACLK		8

#define CLK_GOUT_TREX_D_CORE_GCLK		9

#define CLK_GOUT_TREX_D_CORE_PCLK		10

#define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE	11

#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE	12

#define CLK_GOUT_TREX_P_CORE_PCLK		13

#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE	14

#define CORE_NR_CLK				15



/* CMU_PERI */

#define CLK_MOUT_PERI_BUS_USER		1
@@ -112,4 +134,18 @@ 
#define CLK_GOUT_WDT1_PCLK		43

#define PERI_NR_CLK			44



/* CMU_FSYS */

#define CLK_MOUT_FSYS_BUS_USER		1

#define CLK_MOUT_FSYS_MMC_CARD_USER	2

#define CLK_MOUT_FSYS_MMC_EMBD_USER	3

#define CLK_MOUT_FSYS_MMC_SDIO_USER	4

#define CLK_MOUT_FSYS_USB30DRD_USER	4

#define CLK_GOUT_MMC_CARD_ACLK		5

#define CLK_GOUT_MMC_CARD_SDCLKIN	6

#define CLK_GOUT_MMC_EMBD_ACLK		7

#define CLK_GOUT_MMC_EMBD_SDCLKIN	8

#define CLK_GOUT_MMC_SDIO_ACLK		9

#define CLK_GOUT_MMC_SDIO_SDCLKIN	10

#define FSYS_NR_CLK			11



#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */