Commit 1a4772d9 authored by Roy Sun's avatar Roy Sun Committed by Alex Deucher
Browse files

drm/amdgpu: Change the imprecise function name 



The callback functions are used for SRIOV read/write instead
of just for rlcg read/write

Signed-off-by: default avatarRoy Sun <Roy.Sun@amd.com>
Reviewed-by: default avatarZhou pengju <pengju.zhou@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f72ac409

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −1
Original line number Diff line number Diff line
@@ -563,7 +563,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 
	    adev->gfx.rlc.funcs &&

	    adev->gfx.rlc.funcs->is_rlcg_access_range) {

		if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))

			return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0, 0);

			return adev->gfx.rlc.funcs->sriov_wreg(adev, reg, v, 0, 0);

	} else {

		writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h

+2 −2
Original line number Diff line number Diff line
@@ -127,8 +127,8 @@ struct amdgpu_rlc_funcs { 
	void (*reset)(struct amdgpu_device *adev);

	void (*start)(struct amdgpu_device *adev);

	void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid);

	void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32 acc_flags, u32 hwip);

	u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip);

	void (*sriov_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32 acc_flags, u32 hwip);

	u32 (*sriov_rreg)(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip);

	bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);

};

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+4 −4
Original line number Diff line number Diff line
@@ -1538,7 +1538,7 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32 
	return ret;

}



static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip)

static void gfx_v10_sriov_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip)

{

	u32 rlcg_flag;
@@ -1554,7 +1554,7 @@ static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, 
		WREG32(offset, value);

}



static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip)

static u32 gfx_v10_sriov_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip)

{

	u32 rlcg_flag;
@@ -8268,8 +8268,8 @@ static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 
	.reset = gfx_v10_0_rlc_reset,

	.start = gfx_v10_0_rlc_start,

	.update_spm_vmid = gfx_v10_0_update_spm_vmid,

	.rlcg_wreg = gfx_v10_rlcg_wreg,

	.rlcg_rreg = gfx_v10_rlcg_rreg,

	.sriov_wreg = gfx_v10_sriov_wreg,

	.sriov_rreg = gfx_v10_sriov_rreg,

	.is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,

};

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+2 −2
Original line number Diff line number Diff line
@@ -787,7 +787,7 @@ static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 f 


}



static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,

static void gfx_v9_0_sriov_wreg(struct amdgpu_device *adev, u32 offset,

			       u32 v, u32 acc_flags, u32 hwip)

{

	if ((acc_flags & AMDGPU_REGS_RLC) &&
@@ -5131,7 +5131,7 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 
	.reset = gfx_v9_0_rlc_reset,

	.start = gfx_v9_0_rlc_start,

	.update_spm_vmid = gfx_v9_0_update_spm_vmid,

	.rlcg_wreg = gfx_v9_0_rlcg_wreg,

	.sriov_wreg = gfx_v9_0_sriov_wreg,

	.is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,

};

drivers/gpu/drm/amd/amdgpu/soc15_common.h

+4 −4
Original line number Diff line number Diff line
@@ -28,13 +28,13 @@ 
#define SOC15_REG_OFFSET(ip, inst, reg)	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)



#define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \

	((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->rlcg_wreg) ? \

	 adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \

	((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->sriov_wreg) ? \

	 adev->gfx.rlc.funcs->sriov_wreg(adev, reg, value, flag, hwip) : \

	 WREG32(reg, value))



#define __RREG32_SOC15_RLC__(reg, flag, hwip) \

	((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->rlcg_rreg) ? \

	 adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \

	((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->sriov_rreg) ? \

	 adev->gfx.rlc.funcs->sriov_rreg(adev, reg, flag, hwip) : \

	 RREG32(reg))



#define WREG32_FIELD15(ip, idx, reg, field, val)	\