Commit 1675c3a2 authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: stop disable the scheduler during HW fini 



When we stop the HW for example for GPU reset we should not stop the
front-end scheduler. Otherwise we run into intermediate failures during
command submission.

The scheduler should only be stopped in very few cases:
1. We can't get the hardware working in ring or IB test after a GPU reset.
2. The KIQ scheduler is not used in the front-end and should be disabled during GPU reset.
3. In amdgpu_ring_fini() when the driver unloads.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarNirmoy Das <nirmoy.das@amd.com>
Test-by: default avatarDennis Li <dennis.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6b6706cd

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

+0 −2
Original line number Diff line number Diff line
@@ -320,8 +320,6 @@ static void cik_sdma_gfx_stop(struct amdgpu_device *adev) 
		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);

	}

	sdma0->sched.ready = false;

	sdma1->sched.ready = false;

}



/**

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+0 −8
Original line number Diff line number Diff line
@@ -2442,10 +2442,6 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 
	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);

	if (!enable) {

		for (i = 0; i < adev->gfx.num_gfx_rings; i++)

			adev->gfx.gfx_ring[i].sched.ready = false;

	}

	WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);



	for (i = 0; i < adev->usec_timeout; i++) {
@@ -2924,16 +2920,12 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 


static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)

{

	int i;



	if (enable) {

		WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);

	} else {

		WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,

			     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |

			      CP_MEC_CNTL__MEC_ME2_HALT_MASK));

		for (i = 0; i < adev->gfx.num_compute_rings; i++)

			adev->gfx.compute_ring[i].sched.ready = false;

		adev->gfx.kiq.ring.sched.ready = false;

	}

	udelay(50);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+0 −5
Original line number Diff line number Diff line
@@ -1951,7 +1951,6 @@ static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 


static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)

{

	int i;

	if (enable) {

		WREG32(mmCP_ME_CNTL, 0);

	} else {
@@ -1959,10 +1958,6 @@ static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 
				      CP_ME_CNTL__PFP_HALT_MASK |

				      CP_ME_CNTL__CE_HALT_MASK));

		WREG32(mmSCRATCH_UMSK, 0);

		for (i = 0; i < adev->gfx.num_gfx_rings; i++)

			adev->gfx.gfx_ring[i].sched.ready = false;

		for (i = 0; i < adev->gfx.num_compute_rings; i++)

			adev->gfx.compute_ring[i].sched.ready = false;

	}

	udelay(50);

}

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+9 −16
Original line number Diff line number Diff line
@@ -2432,15 +2432,12 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 
 */

static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)

{

	int i;



	if (enable) {

	if (enable)

		WREG32(mmCP_ME_CNTL, 0);

	} else {

		WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));

		for (i = 0; i < adev->gfx.num_gfx_rings; i++)

			adev->gfx.gfx_ring[i].sched.ready = false;

	}

	else

		WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |

				      CP_ME_CNTL__PFP_HALT_MASK |

				      CP_ME_CNTL__CE_HALT_MASK));

	udelay(50);

}
@@ -2701,15 +2698,11 @@ static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 
 */

static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)

{

	int i;



	if (enable) {

	if (enable)

		WREG32(mmCP_MEC_CNTL, 0);

	} else {

		WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));

		for (i = 0; i < adev->gfx.num_compute_rings; i++)

			adev->gfx.compute_ring[i].sched.ready = false;

	}

	else

		WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK |

				       CP_MEC_CNTL__MEC_ME2_HALT_MASK));

	udelay(50);

}

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+0 −7
Original line number Diff line number Diff line
@@ -4122,7 +4122,6 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) 


static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)

{

	int i;

	u32 tmp = RREG32(mmCP_ME_CNTL);



	if (enable) {
@@ -4133,8 +4132,6 @@ static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 
		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);

		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);

		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);

		for (i = 0; i < adev->gfx.num_gfx_rings; i++)

			adev->gfx.gfx_ring[i].sched.ready = false;

	}

	WREG32(mmCP_ME_CNTL, tmp);

	udelay(50);
@@ -4322,14 +4319,10 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) 


static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)

{

	int i;



	if (enable) {

		WREG32(mmCP_MEC_CNTL, 0);

	} else {

		WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));

		for (i = 0; i < adev->gfx.num_compute_rings; i++)

			adev->gfx.compute_ring[i].sched.ready = false;

		adev->gfx.kiq.ring.sched.ready = false;

	}

	udelay(50);