Commit 156c9041 authored by Sudeep Holla's avatar Sudeep Holla
Browse files

arm64: dts: juno: Add cache-level property to L2 caches

Add the missing cache-level property to L2 caches. This is needed if
we need to find the last level cache directly from the device tree cache
node.

Link: https://lore.kernel.org/r/20220629095959.1115587-1-sudeep.holla@arm.com


Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: default avatarLiviu Dudau <liviu.dudau@arm.com>
Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
parent a0bf153f
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+2 −0
Original line number Diff line number Diff line
@@ -192,6 +192,7 @@ A57_L2: l2-cache0 {
			cache-size = <0x200000>;
			cache-line-size = <64>;
			cache-sets = <2048>;
			cache-level = <2>;
		};

		A53_L2: l2-cache1 {
@@ -199,6 +200,7 @@ A53_L2: l2-cache1 {
			cache-size = <0x100000>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-level = <2>;
		};
	};

+2 −0
Original line number Diff line number Diff line
@@ -198,6 +198,7 @@ A72_L2: l2-cache0 {
			cache-size = <0x200000>;
			cache-line-size = <64>;
			cache-sets = <2048>;
			cache-level = <2>;
		};

		A53_L2: l2-cache1 {
@@ -205,6 +206,7 @@ A53_L2: l2-cache1 {
			cache-size = <0x100000>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-level = <2>;
		};
	};

+2 −0
Original line number Diff line number Diff line
@@ -197,6 +197,7 @@ A57_L2: l2-cache0 {
			cache-size = <0x200000>;
			cache-line-size = <64>;
			cache-sets = <2048>;
			cache-level = <2>;
		};

		A53_L2: l2-cache1 {
@@ -204,6 +205,7 @@ A53_L2: l2-cache1 {
			cache-size = <0x100000>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-level = <2>;
		};
	};