Commit 1513e24a authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher
Browse files

drm/amdgpu/mes10.1: implement the ring functions of mes specific 



Implement mes ring functions and set up them.

Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7b2513a1

drivers/gpu/drm/amd/amdgpu/mes_v10_1.c

+43 −0
Original line number Diff line number Diff line
@@ -33,6 +33,47 @@ MODULE_FIRMWARE("amdgpu/navi10_mes.bin"); 


#define MES_EOP_SIZE   2048



static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;



	if (ring->use_doorbell) {

		atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs],

			     ring->wptr);

		WDOORBELL64(ring->doorbell_index, ring->wptr);

	} else {

		BUG();

	}

}



static u64 mes_v10_1_ring_get_rptr(struct amdgpu_ring *ring)

{

	return ring->adev->wb.wb[ring->rptr_offs];

}



static u64 mes_v10_1_ring_get_wptr(struct amdgpu_ring *ring)

{

	u64 wptr;



	if (ring->use_doorbell)

		wptr = atomic64_read((atomic64_t *)

				     &ring->adev->wb.wb[ring->wptr_offs]);

	else

		BUG();

	return wptr;

}



static const struct amdgpu_ring_funcs mes_v10_1_ring_funcs = {

	.type = AMDGPU_RING_TYPE_MES,

	.align_mask = 1,

	.nop = 0,

	.support_64bit_ptrs = true,

	.get_rptr = mes_v10_1_ring_get_rptr,

	.get_wptr = mes_v10_1_ring_get_wptr,

	.set_wptr = mes_v10_1_ring_set_wptr,

	.insert_nop = amdgpu_ring_insert_nop,

};



static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes,

				  struct mes_add_queue_input *input)

{
@@ -315,6 +356,8 @@ static int mes_v10_1_ring_init(struct amdgpu_device *adev) 


	ring = &adev->mes.ring;



	ring->funcs = &mes_v10_1_ring_funcs;



	ring->me = 3;

	ring->pipe = 0;

	ring->queue = 0;