Commit 143b11c0 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6

parents af01d537 18c8adeb

drivers/net/wireless/ath9k/ath9k.h

+20 −35
Original line number Diff line number Diff line
@@ -144,6 +144,7 @@ struct ath_desc { 
#define ATH9K_TXDESC_EXT_AND_CTL	0x0080

#define ATH9K_TXDESC_VMF		0x0100

#define ATH9K_TXDESC_FRAG_IS_ON 	0x0200

#define ATH9K_TXDESC_CAB		0x0400



#define ATH9K_RXDESC_INTREQ		0x0020
@@ -564,8 +565,6 @@ enum ath9k_cipher { 
#define CTL_5GHT40              8



#define AR_EEPROM_MAC(i)        (0x1d+(i))

#define EEP_SCALE       100

#define EEP_DELTA       10



#define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c

#define AR_EEPROM_RFSILENT_GPIO_SEL_S   2
@@ -606,9 +605,6 @@ struct ath9k_country_entry { 
#define REG_CLR_BIT(_a, _r, _f) \

	REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)



#define ATH9K_COMP_BUF_MAX_SIZE   9216

#define ATH9K_COMP_BUF_ALIGN_SIZE 512



#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS   0x00000001



#define INIT_AIFS       2
@@ -632,12 +628,6 @@ struct ath9k_country_entry { 
				 (IEEE80211_WEP_IVLEN +		\

				  IEEE80211_WEP_KIDLEN +	\

				  IEEE80211_WEP_CRCLEN))

#define IEEE80211_MAX_LEN       (2300 + FCS_LEN +		\

				 (IEEE80211_WEP_IVLEN +		\

				  IEEE80211_WEP_KIDLEN +	\

				  IEEE80211_WEP_CRCLEN))



#define MAX_REG_ADD_COUNT   129

#define MAX_RATE_POWER 63



enum ath9k_power_mode {
@@ -707,13 +697,6 @@ enum phytype { 
};

#define PHY_CCK PHY_DS



enum start_adhoc_option {

	START_ADHOC_NO_11A,

	START_ADHOC_PER_11D,

	START_ADHOC_IN_11A,

	START_ADHOC_IN_11B,

};



enum ath9k_tp_scale {

	ATH9K_TP_SCALE_MAX = 0,

	ATH9K_TP_SCALE_50,
@@ -769,14 +752,11 @@ struct ath9k_node_stats { 


#define ATH9K_RSSI_EP_MULTIPLIER  (1<<7)



enum ath9k_gpio_output_mux_type {

	ATH9K_GPIO_OUTPUT_MUX_AS_OUTPUT,

	ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,

	ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,

	ATH9K_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,

	ATH9K_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,

	ATH9K_GPIO_OUTPUT_MUX_NUM_ENTRIES

};

#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0

#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1

#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED     2

#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED    5

#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED      6



enum {

	ATH9K_RESET_POWER_ON,
@@ -790,19 +770,20 @@ struct ath_hal { 
	u32 ah_magic;

	u16 ah_devid;

	u16 ah_subvendorid;

	struct ath_softc *ah_sc;

	void __iomem *ah_sh;

	u16 ah_countryCode;

	u32 ah_macVersion;

	u16 ah_macRev;

	u16 ah_phyRev;

	u16 ah_analog5GhzRev;

	u16 ah_analog2GhzRev;

	u8 ah_decompMask[ATH9K_DECOMP_MASK_SIZE];

	u32 ah_flags;



	void __iomem *ah_sh;

	struct ath_softc *ah_sc;

	enum ath9k_opmode ah_opmode;

	struct ath9k_ops_config ah_config;

	struct ath9k_hw_capabilities ah_caps;



	u16 ah_countryCode;

	u32 ah_flags;

	int16_t ah_powerLimit;

	u16 ah_maxPowerLevel;

	u32 ah_tpScale;
@@ -812,15 +793,16 @@ struct ath_hal { 
	u16 ah_currentRD5G;

	u16 ah_currentRD2G;

	char ah_iso[4];

	enum start_adhoc_option ah_adHocMode;

	bool ah_commonMode;



	struct ath9k_channel ah_channels[150];

	u32 ah_nchan;

	struct ath9k_channel *ah_curchan;

	u32 ah_nchan;



	u16 ah_rfsilent;

	bool ah_rfkillEnabled;

	bool ah_isPciExpress;

	u16 ah_txTrigLevel;



#ifndef ATH_NF_PER_CHAN

	struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];

#endif
@@ -853,7 +835,7 @@ bool ath9k_regd_init_channels(struct ath_hal *ah, 
u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);

enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah,

				     enum ath9k_int ints);

bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode,

bool ath9k_hw_reset(struct ath_hal *ah,

		    struct ath9k_channel *chan,

		    enum ath9k_ht_macmode macmode,

		    u8 txchainmask, u8 rxchainmask,
@@ -1018,4 +1000,7 @@ void ath9k_hw_get_channel_centers(struct ath_hal *ah, 
bool ath9k_get_channel_edges(struct ath_hal *ah,

			     u16 flags, u16 *low,

			     u16 *high);

void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,

			u32 ah_signal_type);

void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 value);

#endif

drivers/net/wireless/ath9k/beacon.c

+89 −170
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ static int ath_beaconq_config(struct ath_softc *sc) 
	struct ath9k_tx_queue_info qi;



	ath9k_hw_get_txq_props(ah, sc->sc_bhalq, &qi);

	if (sc->sc_opmode == ATH9K_M_HOSTAP) {

	if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) {

		/* Always burst out beacon and CAB traffic. */

		qi.tqi_aifs = 1;

		qi.tqi_cwmin = 0;
@@ -85,7 +85,7 @@ static void ath_beacon_setup(struct ath_softc *sc, 


	flags = ATH9K_TXDESC_NOACK;



	if (sc->sc_opmode == ATH9K_M_IBSS &&

	if (sc->sc_ah->ah_opmode == ATH9K_M_IBSS &&

	    (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) {

		ds->ds_link = bf->bf_daddr; /* self-linked */

		flags |= ATH9K_TXDESC_VEOL;
@@ -111,24 +111,24 @@ static void ath_beacon_setup(struct ath_softc *sc, 
	rix = 0;

	rt = sc->sc_currates;

	rate = rt->info[rix].rateCode;

	if (sc->sc_flags & ATH_PREAMBLE_SHORT)

	if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)

		rate |= rt->info[rix].shortPreamble;



	ath9k_hw_set11n_txdesc(ah, ds

			      , skb->len + FCS_LEN /* frame length */

			      , ATH9K_PKT_TYPE_BEACON /* Atheros packet type */

			      , avp->av_btxctl.txpower /* txpower XXX */

			      , ATH9K_TXKEYIX_INVALID /* no encryption */

			      , ATH9K_KEY_TYPE_CLEAR /* no encryption */

			      , flags /* no ack, veol for beacons */

	ath9k_hw_set11n_txdesc(ah, ds,

			       skb->len + FCS_LEN, /* frame length */

			       ATH9K_PKT_TYPE_BEACON, /* Atheros packet type */

			       avp->av_btxctl.txpower, /* txpower XXX */

			       ATH9K_TXKEYIX_INVALID, /* no encryption */

			       ATH9K_KEY_TYPE_CLEAR, /* no encryption */

			       flags /* no ack, veol for beacons */

		);



	/* NB: beacon's BufLen must be a multiple of 4 bytes */

	ath9k_hw_filltxdesc(ah, ds

			   , roundup(skb->len, 4) /* buffer length */

			   , true /* first segment */

			   , true /* last segment */

			   , ds /* first descriptor */

	ath9k_hw_filltxdesc(ah, ds,

			    roundup(skb->len, 4), /* buffer length */

			    true, /* first segment */

			    true, /* last segment */

			    ds /* first descriptor */

		);



	memzero(series, sizeof(struct ath9k_11n_rate_series) * 4);
@@ -140,55 +140,6 @@ static void ath_beacon_setup(struct ath_softc *sc, 
		ctsrate, ctsduration, series, 4, 0);

}



/* Move everything from the vap's mcast queue to the hardware cab queue.

 * Caller must hold mcasq lock and cabq lock

 * XXX MORE_DATA bit?

 */

static void empty_mcastq_into_cabq(struct ath_hal *ah,

	struct ath_txq *mcastq, struct ath_txq *cabq)

{

	struct ath_buf *bfmcast;



	BUG_ON(list_empty(&mcastq->axq_q));



	bfmcast = list_first_entry(&mcastq->axq_q, struct ath_buf, list);



	/* link the descriptors */

	if (!cabq->axq_link)

		ath9k_hw_puttxbuf(ah, cabq->axq_qnum, bfmcast->bf_daddr);

	else

		*cabq->axq_link = bfmcast->bf_daddr;



	/* append the private vap mcast list to  the cabq */



	cabq->axq_depth	+= mcastq->axq_depth;

	cabq->axq_totalqueued += mcastq->axq_totalqueued;

	cabq->axq_linkbuf = mcastq->axq_linkbuf;

	cabq->axq_link = mcastq->axq_link;

	list_splice_tail_init(&mcastq->axq_q, &cabq->axq_q);

	mcastq->axq_depth = 0;

	mcastq->axq_totalqueued = 0;

	mcastq->axq_linkbuf = NULL;

	mcastq->axq_link = NULL;

}



/* This is only run at DTIM. We move everything from the vap's mcast queue

 * to the hardware cab queue. Caller must hold the mcastq lock. */

static void trigger_mcastq(struct ath_hal *ah,

	struct ath_txq *mcastq, struct ath_txq *cabq)

{

	spin_lock_bh(&cabq->axq_lock);



	if (!list_empty(&mcastq->axq_q))

		empty_mcastq_into_cabq(ah, mcastq, cabq);



	/* cabq is gated by beacon so it is safe to start here */

	if (!list_empty(&cabq->axq_q))

		ath9k_hw_txstart(ah, cabq->axq_qnum);



	spin_unlock_bh(&cabq->axq_lock);

}



/*

 *  Generate beacon frame and queue cab data for a vap.

 *
@@ -199,19 +150,14 @@ static void trigger_mcastq(struct ath_hal *ah, 
*/

static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)

{

	struct ath_hal *ah = sc->sc_ah;

	struct ath_buf *bf;

	struct ath_vap *avp;

	struct sk_buff *skb;

	int cabq_depth;

	int mcastq_depth;

	int is_beacon_dtim = 0;

	unsigned int curlen;

	struct ath_txq *cabq;

	struct ath_txq *mcastq;

	struct ieee80211_tx_info *info;

	avp = sc->sc_vaps[if_id];



	mcastq = &avp->av_mcastq;

	cabq = sc->sc_cabq;



	ASSERT(avp);
@@ -223,32 +169,33 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) 
	}

	bf = avp->av_bcbuf;

	skb = (struct sk_buff *) bf->bf_mpdu;

	if (skb) {

		pci_unmap_single(sc->pdev, bf->bf_dmacontext,

				 skb_end_pointer(skb) - skb->head,

				 PCI_DMA_TODEVICE);

	}



	skb = ieee80211_beacon_get(sc->hw, avp->av_if_data);

	bf->bf_mpdu = skb;

	if (skb == NULL)

		return NULL;

	info = IEEE80211_SKB_CB(skb);

	if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {

		/*

	 * Update dynamic beacon contents.  If this returns

	 * non-zero then we need to remap the memory because

	 * the beacon frame changed size (probably because

	 * of the TIM bitmap).

		 * TODO: make sure the seq# gets assigned properly (vs. other

		 * TX frames)

		 */

	curlen = skb->len;



	/* XXX: spin_lock_bh should not be used here, but sparse bitches

	 * otherwise. We should fix sparse :) */

	spin_lock_bh(&mcastq->axq_lock);

	mcastq_depth = avp->av_mcastq.axq_depth;



	if (ath_update_beacon(sc, if_id, &avp->av_boff, skb, mcastq_depth) ==

	    1) {

		ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,

				     get_dma_mem_context(bf, bf_dmacontext));

		bf->bf_buf_addr = ath_skb_map_single(sc, skb, PCI_DMA_TODEVICE,

			get_dma_mem_context(bf, bf_dmacontext));

	} else {

		pci_dma_sync_single_for_cpu(sc->pdev,

					    bf->bf_buf_addr,

					    skb_tailroom(skb),

					    PCI_DMA_TODEVICE);

		struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;

		sc->seq_no += 0x10;

		hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);

		hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);

	}

	bf->bf_buf_addr = bf->bf_dmacontext =

		pci_map_single(sc->pdev, skb->data,

			       skb_end_pointer(skb) - skb->head,

			       PCI_DMA_TODEVICE);



	skb = ieee80211_get_buffered_bc(sc->hw, avp->av_if_data);



	/*

	 * if the CABQ traffic from previous DTIM is pending and the current
@@ -262,9 +209,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) 
	cabq_depth = cabq->axq_depth;

	spin_unlock_bh(&cabq->axq_lock);



	is_beacon_dtim = avp->av_boff.bo_tim[4] & 1;



	if (mcastq_depth && is_beacon_dtim && cabq_depth) {

	if (skb && cabq_depth) {

		/*

		 * Unlock the cabq lock as ath_tx_draintxq acquires

		 * the lock again which is a common function and that
@@ -284,10 +229,11 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) 
	 * Enable the CAB queue before the beacon queue to

	 * insure cab frames are triggered by this beacon.

	 */

	if (is_beacon_dtim)

		trigger_mcastq(ah, mcastq, cabq);

	while (skb) {

		ath_tx_cabq(sc, skb);

		skb = ieee80211_get_buffered_bc(sc->hw, avp->av_if_data);

	}



	spin_unlock_bh(&mcastq->axq_lock);

	return bf;

}
@@ -375,7 +321,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) 
				struct ath_buf, list);

		list_del(&avp->av_bcbuf->list);



		if (sc->sc_opmode == ATH9K_M_HOSTAP ||

		if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||

		    !(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) {

			int slot;

			/*
@@ -408,8 +354,9 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) 
	bf = avp->av_bcbuf;

	if (bf->bf_mpdu != NULL) {

		skb = (struct sk_buff *)bf->bf_mpdu;

		ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,

				     get_dma_mem_context(bf, bf_dmacontext));

		pci_unmap_single(sc->pdev, bf->bf_dmacontext,

				 skb_end_pointer(skb) - skb->head,

				 PCI_DMA_TODEVICE);

		dev_kfree_skb_any(skb);

		bf->bf_mpdu = NULL;

	}
@@ -418,7 +365,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) 
	 * NB: the beacon data buffer must be 32-bit aligned;

	 * we assume the wbuf routines will return us something

	 * with this alignment (perhaps should assert).

	 * FIXME: Fill avp->av_boff.bo_tim,avp->av_btxctl.txpower and

	 * FIXME: Fill avp->av_btxctl.txpower and

	 * avp->av_btxctl.shortPreamble

	 */

	skb = ieee80211_beacon_get(sc->hw, avp->av_if_data);
@@ -439,9 +386,8 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) 
		__le64 val;

		int intval;



		/* FIXME: Use default value for now: Sujith */



		intval = ATH_DEFAULT_BINTVAL;

		intval = sc->hw->conf.beacon_int ?

			sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL;



		/*

		 * The beacon interval is in TU's; the TSF in usecs.
@@ -466,8 +412,10 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) 
		memcpy(&wh[1], &val, sizeof(val));

	}



	bf->bf_buf_addr = ath_skb_map_single(sc, skb, PCI_DMA_TODEVICE,

		get_dma_mem_context(bf, bf_dmacontext));

	bf->bf_buf_addr = bf->bf_dmacontext =

		pci_map_single(sc->pdev, skb->data,

			       skb_end_pointer(skb) - skb->head,

			       PCI_DMA_TODEVICE);

	bf->bf_mpdu = skb;



	return 0;
@@ -493,8 +441,9 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp) 
		bf = avp->av_bcbuf;

		if (bf->bf_mpdu != NULL) {

			struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;

			ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,

				get_dma_mem_context(bf, bf_dmacontext));

			pci_unmap_single(sc->pdev, bf->bf_dmacontext,

					 skb_end_pointer(skb) - skb->head,

					 PCI_DMA_TODEVICE);

			dev_kfree_skb_any(skb);

			bf->bf_mpdu = NULL;

		}
@@ -504,30 +453,6 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp) 
	}

}



/*

 *  Reclaim beacon resources and return buffer to the pool.

 *

 *  This function will free any wbuf frames that are still attached to the

 *  beacon buffers in the ATH object.  Note that this does not de-allocate

 *  any wbuf objects that are in the transmit queue and have not yet returned

 *  to the ATH object.

*/



void ath_beacon_free(struct ath_softc *sc)

{

	struct ath_buf *bf;



	list_for_each_entry(bf, &sc->sc_bbuf, list) {

		if (bf->bf_mpdu != NULL) {

			struct sk_buff *skb = (struct sk_buff *) bf->bf_mpdu;

			ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,

				get_dma_mem_context(bf, bf_dmacontext));

			dev_kfree_skb_any(skb);

			bf->bf_mpdu = NULL;

		}

	}

}



/*

 * Tasklet for Sending Beacons

 *
@@ -540,9 +465,6 @@ void ath_beacon_free(struct ath_softc *sc) 


void ath9k_beacon_tasklet(unsigned long data)

{

#define TSF_TO_TU(_h,_l)					\

	((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))



	struct ath_softc *sc = (struct ath_softc *)data;

	struct ath_hal *ah = sc->sc_ah;

	struct ath_buf *bf = NULL;
@@ -555,7 +477,7 @@ void ath9k_beacon_tasklet(unsigned long data) 
	u32 tsftu;

	u16 intval;



	if (sc->sc_noreset) {

	if (sc->sc_flags & SC_OP_NO_RESET) {

		show_cycles = ath9k_hw_GetMibCycleCountsPct(ah,

							    &rx_clear,

							    &rx_frame,
@@ -577,7 +499,7 @@ void ath9k_beacon_tasklet(unsigned long data) 
		 *      (in that layer).

		 */

		if (sc->sc_bmisscount < BSTUCK_THRESH) {

			if (sc->sc_noreset) {

			if (sc->sc_flags & SC_OP_NO_RESET) {

				DPRINTF(sc, ATH_DBG_BEACON,

					"%s: missed %u consecutive beacons\n",

					__func__, sc->sc_bmisscount);
@@ -605,7 +527,7 @@ void ath9k_beacon_tasklet(unsigned long data) 
					__func__, sc->sc_bmisscount);

			}

		} else if (sc->sc_bmisscount >= BSTUCK_THRESH) {

			if (sc->sc_noreset) {

			if (sc->sc_flags & SC_OP_NO_RESET) {

				if (sc->sc_bmisscount == BSTUCK_THRESH) {

					DPRINTF(sc,

						ATH_DBG_BEACON,
@@ -624,7 +546,7 @@ void ath9k_beacon_tasklet(unsigned long data) 
		return;

	}

	if (sc->sc_bmisscount != 0) {

		if (sc->sc_noreset) {

		if (sc->sc_flags & SC_OP_NO_RESET) {

			DPRINTF(sc,

				ATH_DBG_BEACON,

				"%s: resume beacon xmit after %u misses\n",
@@ -643,8 +565,8 @@ void ath9k_beacon_tasklet(unsigned long data) 
	 * on the tsf to safeguard against missing an swba.

	 */



	/* FIXME: Use default value for now - Sujith */

	intval = ATH_DEFAULT_BINTVAL;

	intval = sc->hw->conf.beacon_int ?

		sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL;



	tsf = ath9k_hw_gettsf64(ah);

	tsftu = TSF_TO_TU(tsf>>32, tsf);
@@ -704,7 +626,6 @@ void ath9k_beacon_tasklet(unsigned long data) 


		sc->ast_be_xmit += bc;     /* XXX per-vap? */

	}

#undef TSF_TO_TU

}



/*
@@ -719,7 +640,7 @@ void ath_bstuck_process(struct ath_softc *sc) 
	DPRINTF(sc, ATH_DBG_BEACON,

		"%s: stuck beacon; resetting (bmiss count %u)\n",

		__func__, sc->sc_bmisscount);

	ath_internal_reset(sc);

	ath_reset(sc, false);

}



/*
@@ -740,8 +661,6 @@ void ath_bstuck_process(struct ath_softc *sc) 


void ath_beacon_config(struct ath_softc *sc, int if_id)

{

#define TSF_TO_TU(_h,_l)					\

	((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))

	struct ath_hal *ah = sc->sc_ah;

	u32 nexttbtt, intval;

	struct ath_beacon_config conf;
@@ -750,7 +669,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) 
	if (if_id != ATH_IF_ID_ANY)

		av_opmode = sc->sc_vaps[if_id]->av_opmode;

	else

		av_opmode = sc->sc_opmode;

		av_opmode = sc->sc_ah->ah_opmode;



	memzero(&conf, sizeof(struct ath_beacon_config));
@@ -760,7 +679,8 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) 
	 * Protocol stack doesn't support dynamic beacon configuration,

	 * use default configurations.

	 */

	conf.beacon_interval = ATH_DEFAULT_BINTVAL;

	conf.beacon_interval = sc->hw->conf.beacon_int ?

		sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL;

	conf.listen_interval = 1;

	conf.dtim_period = conf.beacon_interval;

	conf.dtim_count = 1;
@@ -770,7 +690,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) 
	nexttbtt = TSF_TO_TU(get_unaligned_le32(conf.u.last_tstamp + 4),

			     get_unaligned_le32(conf.u.last_tstamp));

	/* XXX conditionalize multi-bss support? */

	if (sc->sc_opmode == ATH9K_M_HOSTAP) {

	if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) {

		/*

		 * For multi-bss ap support beacons are either staggered

		 * evenly over N slots or burst together.  For the former
@@ -791,7 +711,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) 
	DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",

		__func__, nexttbtt, intval, conf.beacon_interval);

	/* Check for ATH9K_M_HOSTAP and sc_nostabeacons for WDS client */

	if (sc->sc_opmode == ATH9K_M_STA) {

	if (sc->sc_ah->ah_opmode == ATH9K_M_STA) {

		struct ath9k_beacon_state bs;

		u64 tsf;

		u32 tsftu;
@@ -886,19 +806,19 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) 
			"cfp:period %u "

			"maxdur %u "

			"next %u "

			"timoffset %u\n"

			, __func__

			, (unsigned long long)tsf, tsftu

			, bs.bs_intval

			, bs.bs_nexttbtt

			, bs.bs_dtimperiod

			, bs.bs_nextdtim

			, bs.bs_bmissthreshold

			, bs.bs_sleepduration

			, bs.bs_cfpperiod

			, bs.bs_cfpmaxduration

			, bs.bs_cfpnext

			, bs.bs_timoffset

			"timoffset %u\n",

			__func__,

			(unsigned long long)tsf, tsftu,

			bs.bs_intval,

			bs.bs_nexttbtt,

			bs.bs_dtimperiod,

			bs.bs_nextdtim,

			bs.bs_bmissthreshold,

			bs.bs_sleepduration,

			bs.bs_cfpperiod,

			bs.bs_cfpmaxduration,

			bs.bs_cfpnext,

			bs.bs_timoffset

			);



		ath9k_hw_set_interrupts(ah, 0);
@@ -911,7 +831,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) 
		ath9k_hw_set_interrupts(ah, 0);

		if (nexttbtt == intval)

			intval |= ATH9K_BEACON_RESET_TSF;

		if (sc->sc_opmode == ATH9K_M_IBSS) {

		if (sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {

			/*

			 * Pull nexttbtt forward to reflect the current

			 * TSF .
@@ -943,7 +863,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) 
			if (!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL))

				sc->sc_imask |= ATH9K_INT_SWBA;

			ath_beaconq_config(sc);

		} else if (sc->sc_opmode == ATH9K_M_HOSTAP) {

		} else if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) {

			/*

			 * In AP mode we enable the beacon timers and

			 * SWBA interrupts to prepare beacon frames.
@@ -959,11 +879,10 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) 
		 * When using a self-linked beacon descriptor in

		 * ibss mode load it once here.

		 */

		if (sc->sc_opmode == ATH9K_M_IBSS &&

		if (sc->sc_ah->ah_opmode == ATH9K_M_IBSS &&

		    (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL))

			ath_beacon_start_adhoc(sc, 0);

	}

#undef TSF_TO_TU

}



/* Function to collect beacon rssi data and resync beacon if necessary */
@@ -975,5 +894,5 @@ void ath_beacon_sync(struct ath_softc *sc, int if_id) 
	 * beacon frame we just received.

	 */

	ath_beacon_config(sc, if_id);

	sc->sc_beacons = 1;

	sc->sc_flags |= SC_OP_BEACONS;

}

drivers/net/wireless/ath9k/core.c

+73 −233

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/wireless/ath9k/core.h

+111 −137

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/wireless/ath9k/hw.c

+46 −104
Original line number Diff line number Diff line
@@ -85,29 +85,6 @@ static const struct hal_percal_data adc_init_dc_cal = { 
	ath9k_hw_adc_dccal_calibrate

};



static const struct ath_hal ar5416hal = {

	AR5416_MAGIC,

	0,

	0,

	NULL,

	NULL,

	CTRY_DEFAULT,

	0,

	0,

	0,

	0,

	0,

	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

	},

};



static struct ath9k_rate_table ar5416_11a_table = {

	8,

	{0},
@@ -371,7 +348,7 @@ static void ath9k_hw_set_defaults(struct ath_hal *ah) 
	ah->ah_config.intr_mitigation = 0;

}



static inline void ath9k_hw_override_ini(struct ath_hal *ah,

static void ath9k_hw_override_ini(struct ath_hal *ah,

					 struct ath9k_channel *chan)

{

	if (!AR_SREV_5416_V20_OR_LATER(ah)
@@ -381,7 +358,7 @@ static inline void ath9k_hw_override_ini(struct ath_hal *ah, 
	REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);

}



static inline void ath9k_hw_init_bb(struct ath_hal *ah,

static void ath9k_hw_init_bb(struct ath_hal *ah,

			     struct ath9k_channel *chan)

{

	u32 synthDelay;
@@ -397,7 +374,7 @@ static inline void ath9k_hw_init_bb(struct ath_hal *ah, 
	udelay(synthDelay + BASE_ACTIVATE_DELAY);

}



static inline void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,

static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,

					  enum ath9k_opmode opmode)

{

	struct ath_hal_5416 *ahp = AH5416(ah);
@@ -428,7 +405,7 @@ static inline void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, 
	}

}



static inline void ath9k_hw_init_qos(struct ath_hal *ah)

static void ath9k_hw_init_qos(struct ath_hal *ah)

{

	REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);

	REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
@@ -523,7 +500,7 @@ static inline bool ath9k_hw_nvram_read(struct ath_hal *ah, 
		return ath9k_hw_eeprom_read(ah, off, data);

}



static inline bool ath9k_hw_fill_eeprom(struct ath_hal *ah)

static bool ath9k_hw_fill_eeprom(struct ath_hal *ah)

{

	struct ath_hal_5416 *ahp = AH5416(ah);

	struct ar5416_eeprom *eep = &ahp->ah_eeprom;
@@ -790,7 +767,7 @@ ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, 
	return true;

}



static inline int ath9k_hw_check_eeprom(struct ath_hal *ah)

static int ath9k_hw_check_eeprom(struct ath_hal *ah)

{

	u32 sum = 0, el;

	u16 *eepdata;
@@ -1196,11 +1173,12 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, 


	ah = &ahp->ah;



	memcpy(&ahp->ah, &ar5416hal, sizeof(struct ath_hal));



	ah->ah_sc = sc;

	ah->ah_sh = mem;



	ah->ah_magic = AR5416_MAGIC;

	ah->ah_countryCode = CTRY_DEFAULT;



	ah->ah_devid = devid;

	ah->ah_subvendorid = 0;
@@ -1294,7 +1272,7 @@ u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp, 
	}

}



static inline int ath9k_hw_get_radiorev(struct ath_hal *ah)

static int ath9k_hw_get_radiorev(struct ath_hal *ah)

{

	u32 val;

	int i;
@@ -1307,7 +1285,7 @@ static inline int ath9k_hw_get_radiorev(struct ath_hal *ah) 
	return ath9k_hw_reverse_bits(val, 8);

}



static inline int ath9k_hw_init_macaddr(struct ath_hal *ah)

static int ath9k_hw_init_macaddr(struct ath_hal *ah)

{

	u32 sum;

	int i;
@@ -1389,7 +1367,7 @@ static u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, 
	return spur_val;

}



static inline int ath9k_hw_rfattach(struct ath_hal *ah)

static int ath9k_hw_rfattach(struct ath_hal *ah)

{

	bool rfStatus = false;

	int ecode = 0;
@@ -1434,7 +1412,7 @@ static int ath9k_hw_rf_claim(struct ath_hal *ah) 
	return 0;

}



static inline void ath9k_hw_init_pll(struct ath_hal *ah,

static void ath9k_hw_init_pll(struct ath_hal *ah,

			      struct ath9k_channel *chan)

{

	u32 pll;
@@ -1553,7 +1531,7 @@ static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode) 
	}

}



static inline void

static void

ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)

{

	u32 rfMode = 0;
@@ -1623,7 +1601,7 @@ static bool ath9k_hw_set_reset(struct ath_hal *ah, int type) 
	return true;

}



static inline bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)

static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)

{

	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |

		  AR_RTC_FORCE_WAKE_ON_INT);
@@ -1664,7 +1642,7 @@ static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, 
	}

}



static inline

static

struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,

					  struct ath9k_channel *chan)

{
@@ -2098,7 +2076,7 @@ static void ath9k_hw_ani_attach(struct ath_hal *ah) 
		ahp->ah_procPhyErr |= HAL_PROCESS_ANI;

}



static inline void ath9k_hw_ani_setup(struct ath_hal *ah)

static void ath9k_hw_ani_setup(struct ath_hal *ah)

{

	struct ath_hal_5416 *ahp = AH5416(ah);

	int i;
@@ -2822,32 +2800,11 @@ static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah, 
	}

}



static bool ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,

				enum ath9k_gpio_output_mux_type

				halSignalType)

void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,

			 u32 ah_signal_type)

{

	u32 ah_signal_type;

	u32 gpio_shift;



	static u32 MuxSignalConversionTable[] = {



		AR_GPIO_OUTPUT_MUX_AS_OUTPUT,



		AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,



		AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,



		AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,



		AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,

	};



	if ((halSignalType >= 0)

	    && (halSignalType < ARRAY_SIZE(MuxSignalConversionTable)))

		ah_signal_type = MuxSignalConversionTable[halSignalType];

	else

		return false;



	ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);



	gpio_shift = 2 * gpio;
@@ -2856,16 +2813,12 @@ static bool ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, 
		AR_GPIO_OE_OUT,

		(AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),

		(AR_GPIO_OE_OUT_DRV << gpio_shift));



	return true;

}



static bool ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio,

			      u32 val)

void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)

{

	REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),

		AR_GPIO_BIT(gpio));

	return true;

}



static u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
@@ -2883,7 +2836,7 @@ static u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio) 
	}

}



static inline int ath9k_hw_post_attach(struct ath_hal *ah)

static int ath9k_hw_post_attach(struct ath_hal *ah)

{

	int ecode;
@@ -3595,7 +3548,7 @@ static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, 
	return true;

}



static inline void

static void

ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,

				    struct ath9k_channel *chan,

				    struct cal_data_per_freq *pRawDataSet,
@@ -3777,7 +3730,7 @@ ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah, 
	return;

}



static inline bool

static bool

ath9k_hw_set_power_cal_table(struct ath_hal *ah,

			     struct ar5416_eeprom *pEepData,

			     struct ath9k_channel *chan,
@@ -3980,7 +3933,7 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) 
	}

}



static inline void

static void

ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,

				  struct ath9k_channel *chan,

				  struct cal_target_power_leg *powInfo,
@@ -4046,7 +3999,7 @@ ath9k_hw_get_legacy_target_powers(struct ath_hal *ah, 
	}

}



static inline void

static void

ath9k_hw_get_target_powers(struct ath_hal *ah,

			   struct ath9k_channel *chan,

			   struct cal_target_power_ht *powInfo,
@@ -4113,7 +4066,7 @@ ath9k_hw_get_target_powers(struct ath_hal *ah, 
	}

}



static inline u16

static u16

ath9k_hw_get_max_edge_power(u16 freq,

			    struct cal_ctl_edges *pRdEdgesPower,

			    bool is2GHz)
@@ -4143,7 +4096,7 @@ ath9k_hw_get_max_edge_power(u16 freq, 
	return twiceMaxEdgePower;

}



static inline bool

static bool

ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,

				  struct ar5416_eeprom *pEepData,

				  struct ath9k_channel *chan,
@@ -5122,7 +5075,7 @@ static void ath9k_hw_spur_mitigate(struct ath_hal *ah, 
	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);

}



static inline void ath9k_hw_init_chain_masks(struct ath_hal *ah)

static void ath9k_hw_init_chain_masks(struct ath_hal *ah)

{

	struct ath_hal_5416 *ahp = AH5416(ah);

	int rx_chainmask, tx_chainmask;
@@ -5326,7 +5279,7 @@ bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us) 
	}

}



static inline void ath9k_hw_init_user_settings(struct ath_hal *ah)

static void ath9k_hw_init_user_settings(struct ath_hal *ah)

{

	struct ath_hal_5416 *ahp = AH5416(ah);
@@ -5345,7 +5298,7 @@ static inline void ath9k_hw_init_user_settings(struct ath_hal *ah) 
		ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);

}



static inline int

static int

ath9k_hw_process_ini(struct ath_hal *ah,

		     struct ath9k_channel *chan,

		     enum ath9k_ht_macmode macmode)
@@ -5476,7 +5429,7 @@ ath9k_hw_process_ini(struct ath_hal *ah, 
	return 0;

}



static inline void ath9k_hw_setup_calibration(struct ath_hal *ah,

static void ath9k_hw_setup_calibration(struct ath_hal *ah,

					      struct hal_cal_list *currCal)

{

	REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
@@ -5512,7 +5465,7 @@ static inline void ath9k_hw_setup_calibration(struct ath_hal *ah, 
		    AR_PHY_TIMING_CTRL4_DO_CAL);

}



static inline void ath9k_hw_reset_calibration(struct ath_hal *ah,

static void ath9k_hw_reset_calibration(struct ath_hal *ah,

				       struct hal_cal_list *currCal)

{

	struct ath_hal_5416 *ahp = AH5416(ah);
@@ -5532,7 +5485,7 @@ static inline void ath9k_hw_reset_calibration(struct ath_hal *ah, 
	ahp->ah_CalSamples = 0;

}



static inline void

static void

ath9k_hw_per_calibration(struct ath_hal *ah,

			 struct ath9k_channel *ichan,

			 u8 rxchainmask,
@@ -5622,7 +5575,7 @@ static inline bool ath9k_hw_run_init_cals(struct ath_hal *ah, 
	return true;

}



static inline bool

static bool

ath9k_hw_channel_change(struct ath_hal *ah,

			struct ath9k_channel *chan,

			enum ath9k_ht_macmode macmode)
@@ -5799,7 +5752,7 @@ static bool ath9k_hw_iscal_supported(struct ath_hal *ah, 
	return retval;

}



static inline bool ath9k_hw_init_cal(struct ath_hal *ah,

static bool ath9k_hw_init_cal(struct ath_hal *ah,

			      struct ath9k_channel *chan)

{

	struct ath_hal_5416 *ahp = AH5416(ah);
@@ -5861,7 +5814,7 @@ static inline bool ath9k_hw_init_cal(struct ath_hal *ah, 
}





bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode,

bool ath9k_hw_reset(struct ath_hal *ah,

		    struct ath9k_channel *chan,

		    enum ath9k_ht_macmode macmode,

		    u8 txchainmask, u8 rxchainmask,
@@ -5945,7 +5898,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode, 
			else

				ath9k_hw_set_gpio(ah, 9, 1);

		}

		ath9k_hw_cfg_output(ah, 9, ATH9K_GPIO_OUTPUT_MUX_AS_OUTPUT);

		ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);

	}



	ecode = ath9k_hw_process_ini(ah, chan, macmode);
@@ -5975,7 +5928,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode, 
		  | (ah->ah_config.

		     ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)

		  | ahp->ah_staId1Defaults);

	ath9k_hw_set_operating_mode(ah, opmode);

	ath9k_hw_set_operating_mode(ah, ah->ah_opmode);



	REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));

	REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
@@ -6005,13 +5958,11 @@ bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode, 
	for (i = 0; i < ah->ah_caps.total_queues; i++)

		ath9k_hw_resettxqueue(ah, i);



	ath9k_hw_init_interrupt_masks(ah, opmode);

	ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);

	ath9k_hw_init_qos(ah);



	ath9k_hw_init_user_settings(ah);



	ah->ah_opmode = opmode;



	REG_WRITE(ah, AR_STA_ID1,

		  REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
@@ -7678,8 +7629,7 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q) 
	REG_WRITE(ah, AR_DRETRY_LIMIT(q),

		  SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH)

		  | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG)

		  | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)

		);

		  | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));



	REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);

	REG_WRITE(ah, AR_DMISC(q),
@@ -8324,15 +8274,7 @@ struct ath_hal *ath9k_hw_attach(u16 devid, 
		*error = -ENXIO;

		break;

	}

	if (ah != NULL) {

		ah->ah_devid = ah->ah_devid;

		ah->ah_subvendorid = ah->ah_subvendorid;

		ah->ah_macVersion = ah->ah_macVersion;

		ah->ah_macRev = ah->ah_macRev;

		ah->ah_phyRev = ah->ah_phyRev;

		ah->ah_analog5GhzRev = ah->ah_analog5GhzRev;

		ah->ah_analog2GhzRev = ah->ah_analog2GhzRev;

	}



	return ah;

}