Commit 13c0e836 authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher
Browse files

drm/amd/display: Adjust code style for hw_sequencer.h 



[Why&How]
* Rearrange some definitions for consistency
* Drop legacy code

Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0653e02f

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

+0 −17
Original line number Diff line number Diff line
@@ -288,23 +288,6 @@ static void program_cursor_attributes( 
	}

}



#ifndef TRIM_FSFT

/*

 * dc_optimize_timing_for_fsft() - dc to optimize timing

 */

bool dc_optimize_timing_for_fsft(

	struct dc_stream_state *pStream,

	unsigned int max_input_rate_in_khz)

{

	struct dc  *dc;



	dc = pStream->ctx->dc;



	return (dc->hwss.optimize_timing_for_fsft &&

		dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz));

}

#endif



static bool is_subvp_high_refresh_candidate(struct dc_stream_state *stream)

{

	uint32_t refresh_rate;

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

+0 −7
Original line number Diff line number Diff line
@@ -769,9 +769,6 @@ struct dc_crtc_timing_flags { 
	uint32_t LTE_340MCSC_SCRAMBLE:1;



	uint32_t DSC : 1; /* Use DSC with this timing */

#ifndef TRIM_FSFT

	uint32_t FAST_TRANSPORT: 1;

#endif

	uint32_t VBLANK_SYNCHRONIZABLE: 1;

};
@@ -950,10 +947,6 @@ struct dc_crtc_timing { 
	enum dc_aspect_ratio aspect_ratio;

	enum scanning_type scan_type;



#ifndef TRIM_FSFT

	uint32_t fast_transport_output_rate_100hz;

#endif



	struct dc_crtc_timing_flags flags;

	uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */

	struct dc_dsc_config dsc_cfg;

drivers/gpu/drm/amd/display/dc/dc_stream.h

+0 −6
Original line number Diff line number Diff line
@@ -524,12 +524,6 @@ struct dc_stream_status *dc_stream_get_status_from_state( 
struct dc_stream_status *dc_stream_get_status(

	struct dc_stream_state *dc_stream);



#ifndef TRIM_FSFT

bool dc_optimize_timing_for_fsft(

	struct dc_stream_state *pStream,

	unsigned int max_input_rate_in_khz);

#endif



/*******************************************************************************

 * Cursor interfaces - To manages the cursor within a stream

 ******************************************************************************/

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+0 −27
Original line number Diff line number Diff line
@@ -2927,33 +2927,6 @@ void dcn20_fpga_init_hw(struct dc *dc) 
	if (dc->res_pool->hubbub->funcs->init_crb)

		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

}

#ifndef TRIM_FSFT

bool dcn20_optimize_timing_for_fsft(struct dc *dc,

		struct dc_crtc_timing *timing,

		unsigned int max_input_rate_in_khz)

{

	unsigned int old_v_front_porch;

	unsigned int old_v_total;

	unsigned int max_input_rate_in_100hz;

	unsigned long long new_v_total;



	max_input_rate_in_100hz = max_input_rate_in_khz * 10;

	if (max_input_rate_in_100hz < timing->pix_clk_100hz)

		return false;



	old_v_total = timing->v_total;

	old_v_front_porch = timing->v_front_porch;



	timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;

	timing->pix_clk_100hz = max_input_rate_in_100hz;



	new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz);



	timing->v_total = new_v_total;

	timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total);

	return true;

}

#endif



void dcn20_set_disp_pattern_generator(const struct dc *dc,

		struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h

+0 −6
Original line number Diff line number Diff line
@@ -136,12 +136,6 @@ int dcn20_init_sys_ctx(struct dce_hwseq *hws, 
		struct dc *dc,

		struct dc_phy_addr_space_config *pa_config);



#ifndef TRIM_FSFT

bool dcn20_optimize_timing_for_fsft(struct dc *dc,

		struct dc_crtc_timing *timing,

		unsigned int max_input_rate_in_khz);

#endif



void dcn20_set_disp_pattern_generator(const struct dc *dc,

		struct pipe_ctx *pipe_ctx,

		enum controller_dp_test_pattern test_pattern,