Commit 13ae12d9 authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher
Browse files

drm/amdgpu: use register distance member instead of hardcode in gfxhub v2.1 



This patch updates to use register distance member instead of hardcode
in gfxhub v2.1.

Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Tested-by: default avatarAnZhong Huang <anzhong.huang@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1e40eebe

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

+24 −15
Original line number Diff line number Diff line
@@ -49,15 +49,15 @@ u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev) 
void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

				uint64_t page_table_base)

{

	/* two registers distance between mmGCVM_CONTEXT0_* to mmGCVM_CONTEXT1_* */

	int offset = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32

			- mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];



	WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

				offset * vmid, lower_32_bits(page_table_base));

			    hub->ctx_addr_distance * vmid,

			    lower_32_bits(page_table_base));



	WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

				offset * vmid, upper_32_bits(page_table_base));

			    hub->ctx_addr_distance * vmid,

			    upper_32_bits(page_table_base));

}



static void gfxhub_v2_1_init_gart_aperture_regs(struct amdgpu_device *adev)
@@ -207,6 +207,7 @@ static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev) 


static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev)

{

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];

	int i;

	uint32_t tmp;
@@ -236,25 +237,31 @@ static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev) 
		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,

				    !amdgpu_noretry);

		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp);

		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);

		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);

		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,  i*2,

		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL,

				    i * hub->ctx_distance, tmp);

		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,

				    i * hub->ctx_addr_distance, 0);

		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,

				    i * hub->ctx_addr_distance, 0);

		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,

				    i * hub->ctx_addr_distance,

				    lower_32_bits(adev->vm_manager.max_pfn - 1));

		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,

		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,

				    i * hub->ctx_addr_distance,

				    upper_32_bits(adev->vm_manager.max_pfn - 1));

	}

}



static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev)

{

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];

	unsigned i;



	for (i = 0 ; i < 18; ++i) {

		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,

				    2 * i, 0xffffffff);

				    i * hub->eng_addr_distance, 0xffffffff);

		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,

				    2 * i, 0x1f);

				    i * hub->eng_addr_distance, 0x1f);

	}

}
@@ -288,12 +295,14 @@ int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev) 


void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev)

{

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];

	u32 tmp;

	u32 i;



	/* Disable all tables */

	for (i = 0; i < 16; i++)

		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, 0);

		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL,

				    i * hub->ctx_distance, 0);



	/* Setup TLB control */

	tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);