Commit 0ea9e02a authored by Ding Wang's avatar Ding Wang Committed by Alex Deucher
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drm/amd/display: Use DTO as clock on DP if not 



Use DVO as pixel clock for DP before enabling link
PHY. Otherwise, when switching from HDMI passive dongle
to DP on the same connector, the PHY PLL is used as
pixel clock, and CRTC would stop working.

Signed-off-by: default avatarDing Wang <Ding.Wang@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3e183c5f

drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

+25 −0
Original line number Diff line number Diff line
@@ -61,6 +61,31 @@ void dp_enable_link_phy( 
{

	struct link_encoder *link_enc = link->link_enc;



	struct pipe_ctx *pipes =

			link->dc->current_context->res_ctx.pipe_ctx;

	struct clock_source *dp_cs =

			link->dc->res_pool->dp_clock_source;

	unsigned int i;

	/* If the current pixel clock source is not DTO(happens after

	 * switching from HDMI passive dongle to DP on the same connector),

	 * switch the pixel clock source to DTO.

	 */

	for (i = 0; i < MAX_PIPES; i++) {

		if (pipes[i].stream != NULL &&

			pipes[i].stream->sink != NULL &&

			pipes[i].stream->sink->link == link) {

			if (pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {

				pipes[i].clock_source = dp_cs;

				pipes[i].pix_clk_params.requested_pix_clk =

						pipes[i].stream->public.timing.pix_clk_khz;

				pipes[i].clock_source->funcs->program_pix_clk(

							pipes[i].clock_source,

							&pipes[i].pix_clk_params,

							&pipes[i].pll_settings);

			}

		}

	}



	if (dc_is_dp_sst_signal(signal)) {

		if (signal == SIGNAL_TYPE_EDP) {

			link_enc->funcs->power_control(link_enc, true);