Commit 0e088b8f authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Refactor ctg+ trickle feed disable 



Pull the code to disable trickle feed for all primary planes into a
separate function.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent bdad2b2f

drivers/gpu/drm/i915/intel_pm.c

+19 −43
Original line number Diff line number Diff line
@@ -4387,11 +4387,23 @@ static void ibx_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);

}



static void g4x_disable_trickle_feed(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int pipe;



	for_each_pipe(pipe) {

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |

			   DISPPLANE_TRICKLE_FEED_DISABLE);

		intel_flush_display_plane(dev_priv, pipe);

	}

}



static void ironlake_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;

	int pipe;



	/* Required for FBC */

	dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
@@ -4451,12 +4463,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(CACHE_MODE_0,

		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));



	for_each_pipe(pipe) {

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |

			   DISPPLANE_TRICKLE_FEED_DISABLE);

		intel_flush_display_plane(dev_priv, pipe);

	}

	g4x_disable_trickle_feed(dev);



	ibx_init_clock_gating(dev);

}
@@ -4512,7 +4519,6 @@ static void gen6_check_mch_setup(struct drm_device *dev) 
static void gen6_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int pipe;

	uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;



	I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
@@ -4588,12 +4594,7 @@ static void gen6_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |

		   GEN6_MBCTL_ENABLE_BOOT_FETCH);



	for_each_pipe(pipe) {

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |

			   DISPPLANE_TRICKLE_FEED_DISABLE);

		intel_flush_display_plane(dev_priv, pipe);

	}

	g4x_disable_trickle_feed(dev);



	/* The default value should be 0x200 according to docs, but the two

	 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
@@ -4654,7 +4655,6 @@ static void lpt_suspend_hw(struct drm_device *dev) 
static void haswell_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int pipe;



	I915_WRITE(WM3_LP_ILK, 0);

	I915_WRITE(WM2_LP_ILK, 0);
@@ -4680,12 +4680,7 @@ static void haswell_init_clock_gating(struct drm_device *dev) 
			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);



	for_each_pipe(pipe) {

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |

			   DISPPLANE_TRICKLE_FEED_DISABLE);

		intel_flush_display_plane(dev_priv, pipe);

	}

	g4x_disable_trickle_feed(dev);



	/* WaVSRefCountFullforceMissDisable:hsw */

	gen7_setup_fixed_func_scheduler(dev_priv);
@@ -4711,7 +4706,6 @@ static void haswell_init_clock_gating(struct drm_device *dev) 
static void ivybridge_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int pipe;

	uint32_t snpcr;



	I915_WRITE(WM3_LP_ILK, 0);
@@ -4780,12 +4774,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);



	for_each_pipe(pipe) {

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |

			   DISPPLANE_TRICKLE_FEED_DISABLE);

		intel_flush_display_plane(dev_priv, pipe);

	}

	g4x_disable_trickle_feed(dev);



	/* WaMbcDriverBootEnable:ivb */

	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
@@ -4812,7 +4801,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
static void valleyview_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int pipe;



	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
@@ -4885,12 +4873,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 


	I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);



	for_each_pipe(pipe) {

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |

			   DISPPLANE_TRICKLE_FEED_DISABLE);

		intel_flush_display_plane(dev_priv, pipe);

	}

	g4x_disable_trickle_feed(dev);



	I915_WRITE(CACHE_MODE_1,

		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
@@ -4916,7 +4899,6 @@ static void g4x_init_clock_gating(struct drm_device *dev) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t dspclk_gate;

	int pipe;



	I915_WRITE(RENCLK_GATE_D1, 0);

	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
@@ -4934,13 +4916,7 @@ static void g4x_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(CACHE_MODE_0,

		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));



	for_each_pipe(pipe) {

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |

			   DISPPLANE_TRICKLE_FEED_DISABLE);

		intel_flush_display_plane(dev_priv, pipe);

	}



	g4x_disable_trickle_feed(dev);

}



static void crestline_init_clock_gating(struct drm_device *dev)