Commit 0db4bb04 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Florian Fainelli
Browse files

ARM: dts: broadcom: add missing cache properties 



As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:

  bcm963148.dtb: l2-cache0: 'cache-unified' is a required property

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarWilliam Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/r/20230423150943.118576-1-krzysztof.kozlowski@linaro.org


Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent ac9a7868

arch/arm/boot/dts/bcm47622.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ CA7_3: cpu@3 { 
		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm/boot/dts/bcm63148.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ B15_1: cpu@1 { 
		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm/boot/dts/bcm63178.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ CA7_2: cpu@2 { 
		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm/boot/dts/bcm6756.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ CA7_3: cpu@3 { 
		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm/boot/dts/bcm6846.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ CA7_1: cpu@1 { 
		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};