Commit 0bdf09cc authored by Yifan Zhang's avatar Yifan Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: calling address translation functions to simplify codes 



Use amdgpu_gmc_vram_pa to simplify codes.

Signed-off-by: default avatarYifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2e3b2cb9

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

+1 −2
Original line number Diff line number Diff line
@@ -168,8 +168,7 @@ static void gfxhub_v11_5_0_init_system_aperture_regs(struct amdgpu_device *adev) 
		     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);



	/* Set default page address. */

	value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start

		+ adev->vm_manager.vram_base_offset;

	value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);

	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

		     (u32)(value >> 12));

	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

+1 −2
Original line number Diff line number Diff line
@@ -164,8 +164,7 @@ static void gfxhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev) 
		     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);



	/* Set default page address. */

	value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start

		+ adev->vm_manager.vram_base_offset;

	value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);

	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

		     (u32)(value >> 12));

	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

+1 −2
Original line number Diff line number Diff line
@@ -169,8 +169,7 @@ static void gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_device *adev) 
		     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);



	/* Set default page address. */

	value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start

		+ adev->vm_manager.vram_base_offset;

	value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);

	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

		     (u32)(value >> 12));

	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

+1 −2
Original line number Diff line number Diff line
@@ -500,8 +500,7 @@ static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level, 
				 uint64_t *addr, uint64_t *flags)

{

	if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))

		*addr = adev->vm_manager.vram_base_offset + *addr -

			adev->gmc.vram_start;

		*addr = amdgpu_gmc_vram_mc2pa(adev, *addr);

	BUG_ON(*addr & 0xFFFF00000000003FULL);



	if (!adev->gmc.translate_further)

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

+1 −2
Original line number Diff line number Diff line
@@ -189,8 +189,7 @@ static void mmhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev) 
		     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);



	/* Set default page address. */

	value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +

		adev->vm_manager.vram_base_offset;

	value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);

	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

		     (u32)(value >> 12));

	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,