Commit 0b7af1dd authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/reset' 

- Always observe reset delay when waking devices from D3cold, e.g., after
  system sleep, regardless of whether we're allowed to runtime-suspend to
  D3cold (Lukas Wunner)

- Unify reset and resume delays to wait for downstream devices after a
  bridge reset (Lukas Wunner)

- Wait for downstream devices after a DPC-induced bridge reset (Lukas
  Wunner)

* pci/reset:
  PCI/DPC: Await readiness of secondary bus after reset
  PCI: Unify delay handling for reset and resume
  PCI/PM: Observe reset delay irrespective of bridge_d3
parents 08a67024 53b54ad0

drivers/pci/pci-driver.c

+1 −1
Original line number Diff line number Diff line
@@ -572,7 +572,7 @@ static void pci_pm_default_resume_early(struct pci_dev *pci_dev) 


static void pci_pm_bridge_power_up_actions(struct pci_dev *pci_dev)

{

	pci_bridge_wait_for_secondary_bus(pci_dev);

	pci_bridge_wait_for_secondary_bus(pci_dev, "resume", PCI_RESET_WAIT);

	/*

	 * When powering on a bridge from D3cold, the whole hierarchy may be

	 * powered on into D0uninitialized state, resume them to give them a

drivers/pci/pci.c

+25 −34
Original line number Diff line number Diff line
@@ -167,9 +167,6 @@ static int __init pcie_port_pm_setup(char *str) 
}

__setup("pcie_port_pm=", pcie_port_pm_setup);



/* Time to wait after a reset for device to become responsive */

#define PCIE_RESET_READY_POLL_MS 60000



/**

 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children

 * @bus: pointer to PCI bus structure to search
@@ -1174,7 +1171,7 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) 
			return -ENOTTY;

		}



		if (delay > 1000)

		if (delay > PCI_RESET_WAIT)

			pci_info(dev, "not ready %dms after %s; waiting\n",

				 delay - 1, reset_type);
@@ -1183,7 +1180,7 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) 
		pci_read_config_dword(dev, PCI_COMMAND, &id);

	}



	if (delay > 1000)

	if (delay > PCI_RESET_WAIT)

		pci_info(dev, "ready %dms after %s\n", delay - 1,

			 reset_type);
@@ -4948,24 +4945,31 @@ static int pci_bus_max_d3cold_delay(const struct pci_bus *bus) 
/**

 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible

 * @dev: PCI bridge

 * @reset_type: reset type in human-readable form

 * @timeout: maximum time to wait for devices on secondary bus (milliseconds)

 *

 * Handle necessary delays before access to the devices on the secondary

 * side of the bridge are permitted after D3cold to D0 transition.

 * side of the bridge are permitted after D3cold to D0 transition

 * or Conventional Reset.

 *

 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For

 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section

 * 4.3.2.

 *

 * Return 0 on success or -ENOTTY if the first device on the secondary bus

 * failed to become accessible.

 */

void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)

int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,

				      int timeout)

{

	struct pci_dev *child;

	int delay;



	if (pci_dev_is_disconnected(dev))

		return;

		return 0;



	if (!pci_is_bridge(dev) || !dev->bridge_d3)

		return;

	if (!pci_is_bridge(dev))

		return 0;



	down_read(&pci_bus_sem);
@@ -4977,14 +4981,14 @@ void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev) 
	 */

	if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {

		up_read(&pci_bus_sem);

		return;

		return 0;

	}



	/* Take d3cold_delay requirements into account */

	delay = pci_bus_max_d3cold_delay(dev->subordinate);

	if (!delay) {

		up_read(&pci_bus_sem);

		return;

		return 0;

	}



	child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
@@ -4993,14 +4997,12 @@ void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev) 


	/*

	 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before

	 * accessing the device after reset (that is 1000 ms + 100 ms). In

	 * practice this should not be needed because we don't do power

	 * management for them (see pci_bridge_d3_possible()).

	 * accessing the device after reset (that is 1000 ms + 100 ms).

	 */

	if (!pci_is_pcie(dev)) {

		pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);

		msleep(1000 + delay);

		return;

		return 0;

	}



	/*
@@ -5017,11 +5019,11 @@ void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev) 
	 * configuration requests if we only wait for 100 ms (see

	 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).

	 *

	 * Therefore we wait for 100 ms and check for the device presence.

	 * If it is still not present give it an additional 100 ms.

	 * Therefore we wait for 100 ms and check for the device presence

	 * until the timeout expires.

	 */

	if (!pcie_downstream_port(dev))

		return;

		return 0;



	if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {

		pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
@@ -5032,14 +5034,11 @@ void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev) 
		if (!pcie_wait_for_link_delay(dev, true, delay)) {

			/* Did not train, no need to wait any further */

			pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");

			return;

			return -ENOTTY;

		}

	}



	if (!pci_device_is_present(child)) {

		pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);

		msleep(delay);

	}

	return pci_dev_wait(child, reset_type, timeout - delay);

}



void pci_reset_secondary_bus(struct pci_dev *dev)
@@ -5058,15 +5057,6 @@ void pci_reset_secondary_bus(struct pci_dev *dev) 


	ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;

	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);



	/*

	 * Trhfa for conventional PCI is 2^25 clock cycles.

	 * Assuming a minimum 33MHz clock this results in a 1s

	 * delay before we can consider subordinate devices to

	 * be re-initialized.  PCIe has some ways to shorten this,

	 * but we don't make use of them yet.

	 */

	ssleep(1);

}



void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
@@ -5085,7 +5075,8 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev) 
{

	pcibios_reset_secondary_bus(dev);



	return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);

	return pci_bridge_wait_for_secondary_bus(dev, "bus reset",

						 PCIE_RESET_READY_POLL_MS);

}

EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);

drivers/pci/pci.h

+15 −1
Original line number Diff line number Diff line
@@ -64,6 +64,19 @@ struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 
#define PCI_PM_D3HOT_WAIT       10	/* msec */

#define PCI_PM_D3COLD_WAIT      100	/* msec */



/*

 * Following exit from Conventional Reset, devices must be ready within 1 sec

 * (PCIe r6.0 sec 6.6.1).  A D3cold to D0 transition implies a Conventional

 * Reset (PCIe r6.0 sec 5.8).

 */

#define PCI_RESET_WAIT		1000	/* msec */

/*

 * Devices may extend the 1 sec period through Request Retry Status completions

 * (PCIe r6.0 sec 2.3.1).  The spec does not provide an upper limit, but 60 sec

 * ought to be enough for any device to become responsive.

 */

#define PCIE_RESET_READY_POLL_MS 60000	/* msec */



void pci_update_current_state(struct pci_dev *dev, pci_power_t state);

void pci_refresh_power_state(struct pci_dev *dev);

int pci_power_up(struct pci_dev *dev);
@@ -86,8 +99,9 @@ void pci_msi_init(struct pci_dev *dev); 
void pci_msix_init(struct pci_dev *dev);

bool pci_bridge_d3_possible(struct pci_dev *dev);

void pci_bridge_d3_update(struct pci_dev *dev);

void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);

void pci_bridge_reconfigure_ltr(struct pci_dev *dev);

int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,

				      int timeout);



static inline void pci_wakeup_event(struct pci_dev *dev)

{

drivers/pci/pcie/dpc.c

+2 −2
Original line number Diff line number Diff line
@@ -170,8 +170,8 @@ pci_ers_result_t dpc_reset_link(struct pci_dev *pdev) 
	pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,

			      PCI_EXP_DPC_STATUS_TRIGGER);



	if (!pcie_wait_for_link(pdev, true)) {

		pci_info(pdev, "Data Link Layer Link Active not set in 1000 msec\n");

	if (pci_bridge_wait_for_secondary_bus(pdev, "DPC",

					      PCIE_RESET_READY_POLL_MS)) {

		clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);

		ret = PCI_ERS_RESULT_DISCONNECT;

	} else {