Commit 091aec0b authored by Andrey Grodzovsky's avatar Andrey Grodzovsky Committed by Alex Deucher
Browse files

drm/amd: Use newly added interrupt source defs for VI v3. 



v2: Rebase
v3: Use defines for CP_SQ and CP_ECC_ERROR interrupts.

Signed-off-by: default avatarAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 530e7a66

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

+4 −2
Original line number Diff line number Diff line
@@ -41,6 +41,8 @@ 
#include "gmc/gmc_8_1_d.h"

#include "gmc/gmc_8_1_sh_mask.h"



#include "ivsrcid/ivsrcid_vislands30.h"



static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);

static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -2737,14 +2739,14 @@ static int dce_v10_0_sw_init(void *handle) 
			return r;

	}



	for (i = 8; i < 20; i += 2) {

	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {

		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);

		if (r)

			return r;

	}



	/* HPD hotplug */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);

	if (r)

		return r;

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

+4 −2
Original line number Diff line number Diff line
@@ -41,6 +41,8 @@ 
#include "gmc/gmc_8_1_d.h"

#include "gmc/gmc_8_1_sh_mask.h"



#include "ivsrcid/ivsrcid_vislands30.h"



static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);

static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -2858,14 +2860,14 @@ static int dce_v11_0_sw_init(void *handle) 
			return r;

	}



	for (i = 8; i < 20; i += 2) {

	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {

		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);

		if (r)

			return r;

	}



	/* HPD hotplug */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);

	if (r)

		return r;

drivers/gpu/drm/amd/amdgpu/dce_virtual.c

+2 −1
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ 
#include "dce_v10_0.h"

#include "dce_v11_0.h"

#include "dce_virtual.h"

#include "ivsrcid/ivsrcid_vislands30.h"



#define DCE_VIRTUAL_VBLANK_PERIOD 16666666
@@ -378,7 +379,7 @@ static int dce_virtual_sw_init(void *handle) 
	int r, i;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 229, &adev->crtc_irq);

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER, &adev->crtc_irq);

	if (r)

		return r;

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+8 −6
Original line number Diff line number Diff line
@@ -51,6 +51,8 @@ 


#include "smu/smu_7_1_3_d.h"



#include "ivsrcid/ivsrcid_vislands30.h"



#define GFX8_NUM_GFX_RINGS     1

#define GFX8_MEC_HPD_SIZE 2048
@@ -2047,35 +2049,35 @@ static int gfx_v8_0_sw_init(void *handle) 
	adev->gfx.mec.num_queue_per_pipe = 8;



	/* KIQ event */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 178, &adev->gfx.kiq.irq);

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_INT_IB2, &adev->gfx.kiq.irq);

	if (r)

		return r;



	/* EOP Event */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);

	if (r)

		return r;



	/* Privileged reg */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184,

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,

			      &adev->gfx.priv_reg_irq);

	if (r)

		return r;



	/* Privileged inst */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185,

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,

			      &adev->gfx.priv_inst_irq);

	if (r)

		return r;



	/* Add CP EDC/ECC irq  */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 197,

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,

			      &adev->gfx.cp_ecc_error_irq);

	if (r)

		return r;



	/* SQ interrupts. */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 239,

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,

			      &adev->gfx.sq_irq);

	if (r) {

		DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

+4 −2
Original line number Diff line number Diff line
@@ -43,6 +43,8 @@ 


#include "amdgpu_atombios.h"



#include "ivsrcid/ivsrcid_vislands30.h"



static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);

static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);

static int gmc_v7_0_wait_for_idle(void *handle);
@@ -996,11 +998,11 @@ static int gmc_v7_0_sw_init(void *handle) 
		adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);

	}



	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);

	if (r)

		return r;



	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);

	if (r)

		return r;