Commit 09159b80 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-arm-dt-for-v5.14-tag1' of... 

Merge tag 'renesas-arm-dt-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.14

  - GPIO extender support for the Falcon development board,
  - Switches support for the ALT development board,
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm-dt-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  ARM: dts: alt: Add SW2 as GPIO keys
  ARM: dts: renesas: Move enable-method to CPU nodes
  arm64: dts: renesas: beacon: Fix USB ref clock references
  arm64: dts: renesas: beacon: Fix USB extal reference
  ARM: dts: rcar-gen1: Correct internal delay for i2c[123]
  arm64: dts: renesas: eagle: Add x1 clock
  ARM: dts: koelsch: Rename sw2 to keyboard
  ARM: dts: r8a7779, marzen: Fix DU clock names
  arm64: dts: renesas: v3msk: Fix memory size
  arm64: dts: renesas: condor: Switch eMMC bus to 1V8
  arm64: dts: renesas: falcon-csi-dsi: Add GPIO extenders
  arm64: dts: renesas: beacon kit: Setup AVB refclk
  arm64: dts: renesas: Add fck to etheravb-rcar-gen3 clock-names list
  ARM: dts: renesas: Add fck to etheravb-rcar-gen2 clock-names list

Link: https://lore.kernel.org/r/cover.1622188835.git.geert+renesas@glider.be


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents b7c8bde7 1b32fce4

arch/arm/boot/dts/r8a7742.dtsi

+5 −1
Original line number Diff line number Diff line
@@ -47,7 +47,6 @@ can_clk: can { 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "renesas,apmu";



		cpu0: cpu@0 {

			device_type = "cpu";
@@ -56,6 +55,7 @@ cpu0: cpu@0 { 
			clock-frequency = <1400000000>;

			clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;

			power-domains = <&sysc R8A7742_PD_CA15_CPU0>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;

			capacity-dmips-mhz = <1024>;

			voltage-tolerance = <1>; /* 1% */
@@ -77,6 +77,7 @@ cpu1: cpu@1 { 
			clock-frequency = <1400000000>;

			clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;

			power-domains = <&sysc R8A7742_PD_CA15_CPU1>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;

			capacity-dmips-mhz = <1024>;

			voltage-tolerance = <1>; /* 1% */
@@ -98,6 +99,7 @@ cpu2: cpu@2 { 
			clock-frequency = <1400000000>;

			clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;

			power-domains = <&sysc R8A7742_PD_CA15_CPU2>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;

			capacity-dmips-mhz = <1024>;

			voltage-tolerance = <1>; /* 1% */
@@ -119,6 +121,7 @@ cpu3: cpu@3 { 
			clock-frequency = <1400000000>;

			clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;

			power-domains = <&sysc R8A7742_PD_CA15_CPU3>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;

			capacity-dmips-mhz = <1024>;

			voltage-tolerance = <1>; /* 1% */
@@ -750,6 +753,7 @@ avb: ethernet@e6800000 { 
			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;

			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 812>;

			clock-names = "fck";

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 812>;

			#address-cells = <1>;

arch/arm/boot/dts/r8a7743.dtsi

+3 −1
Original line number Diff line number Diff line
@@ -49,7 +49,6 @@ can_clk: can { 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "renesas,apmu";



		cpu0: cpu@0 {

			device_type = "cpu";
@@ -59,6 +58,7 @@ cpu0: cpu@0 { 
			clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;

			clock-latency = <300000>; /* 300 us */

			power-domains = <&sysc R8A7743_PD_CA15_CPU0>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;



			/* kHz - uV - OPPs unknown yet */
@@ -78,6 +78,7 @@ cpu1: cpu@1 { 
			clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;

			clock-latency = <300000>; /* 300 us */

			power-domains = <&sysc R8A7743_PD_CA15_CPU1>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;



			/* kHz - uV - OPPs unknown yet */
@@ -702,6 +703,7 @@ avb: ethernet@e6800000 { 
			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;

			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 812>;

			clock-names = "fck";

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			resets = <&cpg 812>;

			#address-cells = <1>;

arch/arm/boot/dts/r8a7744.dtsi

+3 −1
Original line number Diff line number Diff line
@@ -49,7 +49,6 @@ can_clk: can { 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "renesas,apmu";



		cpu0: cpu@0 {

			device_type = "cpu";
@@ -59,6 +58,7 @@ cpu0: cpu@0 { 
			clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;

			clock-latency = <300000>; /* 300 us */

			power-domains = <&sysc R8A7744_PD_CA15_CPU0>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;



			/* kHz - uV - OPPs unknown yet */
@@ -78,6 +78,7 @@ cpu1: cpu@1 { 
			clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;

			clock-latency = <300000>; /* 300 us */

			power-domains = <&sysc R8A7744_PD_CA15_CPU1>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;



			/* kHz - uV - OPPs unknown yet */
@@ -702,6 +703,7 @@ avb: ethernet@e6800000 { 
			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;

			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 812>;

			clock-names = "fck";

			power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;

			resets = <&cpg 812>;

			#address-cells = <1>;

arch/arm/boot/dts/r8a7745.dtsi

+3 −1
Original line number Diff line number Diff line
@@ -64,7 +64,6 @@ can_clk: can { 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "renesas,apmu";



		cpu0: cpu@0 {

			device_type = "cpu";
@@ -73,6 +72,7 @@ cpu0: cpu@0 { 
			clock-frequency = <1000000000>;

			clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;

			power-domains = <&sysc R8A7745_PD_CA7_CPU0>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA7>;

		};
@@ -83,6 +83,7 @@ cpu1: cpu@1 { 
			clock-frequency = <1000000000>;

			clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;

			power-domains = <&sysc R8A7745_PD_CA7_CPU1>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA7>;

		};
@@ -645,6 +646,7 @@ avb: ethernet@e6800000 { 
			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;

			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 812>;

			clock-names = "fck";

			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;

			resets = <&cpg 812>;

			#address-cells = <1>;

arch/arm/boot/dts/r8a77470.dtsi

+3 −1
Original line number Diff line number Diff line
@@ -25,7 +25,6 @@ aliases { 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "renesas,apmu";



		cpu0: cpu@0 {

			device_type = "cpu";
@@ -34,6 +33,7 @@ cpu0: cpu@0 { 
			clock-frequency = <1000000000>;

			clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;

			power-domains = <&sysc R8A77470_PD_CA7_CPU0>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA7>;

		};
@@ -44,6 +44,7 @@ cpu1: cpu@1 { 
			clock-frequency = <1000000000>;

			clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;

			power-domains = <&sysc R8A77470_PD_CA7_CPU1>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA7>;

		};
@@ -537,6 +538,7 @@ avb: ethernet@e6800000 { 
			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;

			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 812>;

			clock-names = "fck";

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 812>;

			#address-cells = <1>;