Commit 08ee16e9 authored by Lars Povlsen's avatar Lars Povlsen
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arm64: dts: sparx5: Add SPI controller and associated mmio-mux 



This adds a SPI controller to the Microchip Sparx5 SoC, as well as the
mmio-mux that is required to select the right SPI interface for a
given SPI device.

Signed-off-by: default avatarLars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200824203010.2033-4-lars.povlsen@microchip.com
parent b17400c9

arch/arm64/boot/dts/microchip/sparx5.dtsi

+30 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ / { 
	#size-cells = <1>;



	aliases {

		spi0 = &spi0;

		serial0 = &uart0;

		serial1 = &uart1;

	};
@@ -118,6 +119,22 @@ gic: interrupt-controller@600300000 { 
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		};



		cpu_ctrl: syscon@600000000 {

			compatible = "microchip,sparx5-cpu-syscon", "syscon",

				     "simple-mfd";

			reg = <0x6 0x00000000 0xd0>;

			mux: mux-controller {

				compatible = "mmio-mux";

				#mux-control-cells = <0>;

				/*

				 * SI_OWNER and SI2_OWNER in GENERAL_CTRL

				 * SPI:  value 9 - (SIMC,SIBM) = 0b1001

				 * SPI2: value 6 - (SIBM,SIMC) = 0b0110

				 */

				mux-reg-masks = <0x88 0xf0>;

			};

		};



		uart0: serial@600100000 {

			pinctrl-0 = <&uart_pins>;

			pinctrl-names = "default";
@@ -144,6 +161,19 @@ uart1: serial@600102000 { 
			status = "disabled";

		};



		spi0: spi@600104000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "microchip,sparx5-spi";

			reg = <0x6 0x00104000 0x40>;

			num-cs = <16>;

			reg-io-width = <4>;

			reg-shift = <2>;

			clocks = <&ahb_clk>;

			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};



		timer1: timer@600105000 {

			compatible = "snps,dw-apb-timer";

			reg = <0x6 0x00105000 0x1000>;