Commit 06279f82 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

arm64: dts: renesas: r8a779a0: Add CPU0 core clock 



Describe the clock for the first Cortex-A76 CPU core.
For now no operating points are defined.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/3ace4eea4ff1cdc0f7b8ea7d0433c1063d795785.1654701400.git.geert+renesas@glider.be
parent 650fd1d0

arch/arm64/boot/dts/renesas/r8a779a0.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ a76_0: cpu@0 { 
			device_type = "cpu";

			power-domains = <&sysc R8A779A0_PD_A1E0D0C0>;

			next-level-cache = <&L3_CA76_0>;

			clocks = <&cpg CPG_CORE R8A779A0_CLK_Z0>;

		};



		L3_CA76_0: cache-controller-0 {