Commit 05d6aea3 authored by David Galiffi's avatar David Galiffi Committed by Alex Deucher
Browse files

drm/amd/display: Disable physym clock 



[How & Why]
Disable physym clock when it's not in use.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarEric Yang <Eric.Yang2@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarDavid Galiffi <David.Galiffi@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0015cce5

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h

+6 −2
Original line number Diff line number Diff line
@@ -196,8 +196,12 @@ 
	type HDMISTREAMCLK0_DTO_PHASE;\

	type HDMISTREAMCLK0_DTO_MODULO;\

	type HDMICHARCLK0_GATE_DISABLE;\

	type HDMICHARCLK0_ROOT_GATE_DISABLE;



	type HDMICHARCLK0_ROOT_GATE_DISABLE; \

	type PHYASYMCLK_GATE_DISABLE; \

	type PHYBSYMCLK_GATE_DISABLE; \

	type PHYCSYMCLK_GATE_DISABLE; \

	type PHYDSYMCLK_GATE_DISABLE; \

	type PHYESYMCLK_GATE_DISABLE;



struct dccg_shift {

	DCCG_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c

+52 −10
Original line number Diff line number Diff line
@@ -420,54 +420,89 @@ void dccg31_set_physymclk( 
	/* Force PHYSYMCLK on and Select phyd32clk as the source of clock which is output to PHY through DCIO */

	switch (phy_inst) {

	case 0:

		if (force_enable)

		if (force_enable) {

			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,

					PHYASYMCLK_FORCE_EN, 1,

					PHYASYMCLK_FORCE_SRC_SEL, clk_src);

		else

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYASYMCLK_GATE_DISABLE, 1);

		} else {

			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,

					PHYASYMCLK_FORCE_EN, 0,

					PHYASYMCLK_FORCE_SRC_SEL, 0);

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYASYMCLK_GATE_DISABLE, 0);

		}

		break;

	case 1:

		if (force_enable)

		if (force_enable) {

			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,

					PHYBSYMCLK_FORCE_EN, 1,

					PHYBSYMCLK_FORCE_SRC_SEL, clk_src);

		else

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYBSYMCLK_GATE_DISABLE, 1);

		} else {

			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,

					PHYBSYMCLK_FORCE_EN, 0,

					PHYBSYMCLK_FORCE_SRC_SEL, 0);

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYBSYMCLK_GATE_DISABLE, 0);

		}

		break;

	case 2:

		if (force_enable)

		if (force_enable) {

			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,

					PHYCSYMCLK_FORCE_EN, 1,

					PHYCSYMCLK_FORCE_SRC_SEL, clk_src);

		else

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYCSYMCLK_GATE_DISABLE, 1);

		} else {

			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,

					PHYCSYMCLK_FORCE_EN, 0,

					PHYCSYMCLK_FORCE_SRC_SEL, 0);

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYCSYMCLK_GATE_DISABLE, 0);

		}

		break;

	case 3:

		if (force_enable)

		if (force_enable) {

			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,

					PHYDSYMCLK_FORCE_EN, 1,

					PHYDSYMCLK_FORCE_SRC_SEL, clk_src);

		else

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYDSYMCLK_GATE_DISABLE, 1);

		} else {

			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,

					PHYDSYMCLK_FORCE_EN, 0,

					PHYDSYMCLK_FORCE_SRC_SEL, 0);

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYDSYMCLK_GATE_DISABLE, 0);

		}

		break;

	case 4:

		if (force_enable)

		if (force_enable) {

			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,

					PHYESYMCLK_FORCE_EN, 1,

					PHYESYMCLK_FORCE_SRC_SEL, clk_src);

		else

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYESYMCLK_GATE_DISABLE, 1);

		} else {

			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,

					PHYESYMCLK_FORCE_EN, 0,

					PHYESYMCLK_FORCE_SRC_SEL, 0);

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYESYMCLK_GATE_DISABLE, 0);

		}

		break;

	default:

		BREAK_TO_DEBUGGER();
@@ -629,6 +664,13 @@ void dccg31_init(struct dccg *dccg) 
		dccg31_disable_dpstreamclk(dccg, 3);

	}



	if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {

		dccg31_set_physymclk(dccg, 0, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

		dccg31_set_physymclk(dccg, 1, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

		dccg31_set_physymclk(dccg, 2, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

		dccg31_set_physymclk(dccg, 3, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

		dccg31_set_physymclk(dccg, 4, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

	}

}



static const struct dccg_funcs dccg31_funcs = {

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h

+5 −0
Original line number Diff line number Diff line
@@ -136,6 +136,11 @@ 
	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, mask_sh),\

	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, mask_sh),\

	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_ROOT_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\