Commit 038ff6f5 authored by Sascha Hauer's avatar Sascha Hauer Committed by Chanwoo Choi
Browse files

PM / devfreq: rockchip-dfi: Handle LPDDR2 correctly 

According to the downstream driver the DDRMON_CTRL_LPDDR23 bit must be
set for both LPDDR2 and LPDDR3. Add the missing LPDDR2 case and while
at it turn the if/else if/else into switch/case which makes it easier
to read.

Link: https://lore.kernel.org/all/20231018061714.3553817-12-s.hauer@pengutronix.de/


Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
parent 076b0597

drivers/devfreq/event/rockchip-dfi.c

+9 −2
Original line number Diff line number Diff line
@@ -83,12 +83,19 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) 
		       DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);



	/* set ddr type to dfi */

	if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)

	switch (dfi->ddr_type) {

	case ROCKCHIP_DDRTYPE_LPDDR2:

	case ROCKCHIP_DDRTYPE_LPDDR3:

		writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),

			       dfi_regs + DDRMON_CTRL);

	else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)

		break;

	case ROCKCHIP_DDRTYPE_LPDDR4:

		writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),

			       dfi_regs + DDRMON_CTRL);

		break;

	default:

		break;

	}



	/* enable count, use software mode */

	writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),