Commit 011b514f authored by Aaron Liu's avatar Aaron Liu Committed by Alex Deucher
Browse files

drm/amdgpu: support nbio_7_2_1 for yellow carp 



This patch adds nbio_7_2_1 support yellow carp.

Signed-off-by: default avatarAaron Liu <aaron.liu@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bf9d4e88

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

+104 −38
Original line number Diff line number Diff line
@@ -28,6 +28,25 @@ 
#include "nbio/nbio_7_2_0_sh_mask.h"

#include <uapi/linux/kfd_ioctl.h>



#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC				0x0015

#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC_BASE_IDX		2

#define regBIF_BX0_BIF_FB_EN_YC								0x0100

#define regBIF_BX0_BIF_FB_EN_YC_BASE_IDX					2

#define regBIF1_PCIE_MST_CTRL_3								0x4601c6

#define regBIF1_PCIE_MST_CTRL_3_BASE_IDX					5

#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT \

			0x1b

#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT \

			0x1c

#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK \

			0x08000000L

#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK \

			0x30000000L

#define regBIF1_PCIE_TX_POWER_CTRL_1						0x460187

#define regBIF1_PCIE_TX_POWER_CTRL_1_BASE_IDX				5

#define BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK		0x00000001L

#define BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK	0x00000008L



static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)

{

	WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
@@ -38,7 +57,12 @@ static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev) 


static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)

{

	u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);

	u32 tmp;



	if (adev->asic_type == CHIP_YELLOW_CARP)

		tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);

	else

		tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);



	tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;

	tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
@@ -49,9 +73,17 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev) 
static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)

{

	if (enable)

		if (adev->asic_type == CHIP_YELLOW_CARP)

			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC,

				BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |

				BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);

		else

			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,

				BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |

				BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);

	else

		if (adev->asic_type == CHIP_YELLOW_CARP)

			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);

		else

			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);

}
@@ -218,20 +250,43 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev 
{

	uint32_t def, data;



	if (adev->asic_type == CHIP_YELLOW_CARP) {

		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));

		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))

			data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;

		else

			data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK;



		if (def != data)

			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);



		data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1));

		def = data;

		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))

			data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |

				BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);

		else

			data &= ~(BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |

				BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);



		if (def != data)

			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1),

				data);

	} else {

		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {

		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))

			data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |

				 PCIE_CNTL2__MST_MEM_LS_EN_MASK |

				 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);

	} else {

		else

			data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |

				  PCIE_CNTL2__MST_MEM_LS_EN_MASK |

				  PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);

	}



		if (def != data)

			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);

	}

}



static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev,

					    u32 *flags)
@@ -297,14 +352,25 @@ const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = { 
static void nbio_v7_2_init_registers(struct amdgpu_device *adev)

{

	uint32_t def, data;

	if (adev->asic_type == CHIP_YELLOW_CARP) {

		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3));

		data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,

			CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);

		data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,

			CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);



		if (def != data)

			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);

	} else {

		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));

	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);

	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);

		data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,

			CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);

		data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,

			CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);



		if (def != data)

		WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL),

				 data);

			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);

	}

}



const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {