Commit 011907fd authored by Dennis Li's avatar Dennis Li Committed by Alex Deucher
Browse files

drm/amdgpu: covert ras status to kernel errno 



The original codes use ras status and kernl errno together in the same
function, which is a wrong code style.

Signed-off-by: default avatarDennis Li <Dennis.Li@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 509b9a5b

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+27 −2
Original line number Diff line number Diff line
@@ -1114,6 +1114,31 @@ int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 
	return ret;

}



static int psp_ras_status_to_errno(struct amdgpu_device *adev,

					 enum ta_ras_status ras_status)

{

	int ret = -EINVAL;



	switch (ras_status) {

	case TA_RAS_STATUS__SUCCESS:

		ret = 0;

		break;

	case TA_RAS_STATUS__RESET_NEEDED:

		ret = -EAGAIN;

		break;

	case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:

		dev_warn(adev->dev, "RAS WARN: ras function unavailable\n");

		break;

	case TA_RAS_STATUS__ERROR_ASD_READ_WRITE:

		dev_warn(adev->dev, "RAS WARN: asd read or write failed\n");

		break;

	default:

		dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret);

	}



	return ret;

}



int psp_ras_enable_features(struct psp_context *psp,

		union ta_ras_cmd_input *info, bool enable)

{
@@ -1137,7 +1162,7 @@ int psp_ras_enable_features(struct psp_context *psp, 
	if (ret)

		return -EINVAL;



	return ras_cmd->ras_status;

	return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);

}



static int psp_ras_terminate(struct psp_context *psp)
@@ -1220,7 +1245,7 @@ int psp_ras_trigger_error(struct psp_context *psp, 
	if (amdgpu_ras_intr_triggered())

		return 0;



	return ras_cmd->ras_status;

	return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);

}

// ras end

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+7 −36
Original line number Diff line number Diff line
@@ -586,29 +586,6 @@ struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, 
}

/* obj end */



static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,

					 const char* invoke_type,

					 const char* block_name,

					 enum ta_ras_status ret)

{

	switch (ret) {

	case TA_RAS_STATUS__SUCCESS:

		return;

	case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:

		dev_warn(adev->dev,

			"RAS WARN: %s %s currently unavailable\n",

			invoke_type,

			block_name);

		break;

	default:

		dev_err(adev->dev,

			"RAS ERROR: %s %s error failed ret 0x%X\n",

			invoke_type,

			block_name,

			ret);

	}

}



/* feature ctl begin */

static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,

					 struct ras_common_if *head)
@@ -703,15 +680,10 @@ int amdgpu_ras_feature_enable(struct amdgpu_device *adev, 
	if (!amdgpu_ras_intr_triggered()) {

		ret = psp_ras_enable_features(&adev->psp, info, enable);

		if (ret) {

			amdgpu_ras_parse_status_code(adev,

			dev_err(adev->dev, "ras %s %s failed %d\n",

				enable ? "enable":"disable",

				ras_block_str(head->block),

						    (enum ta_ras_status)ret);

			if (ret == TA_RAS_STATUS__RESET_NEEDED)

				ret = -EAGAIN;

			else

				ret = -EINVAL;



				ret);

			goto out;

		}

	}
@@ -1056,10 +1028,9 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev, 
		ret = -EINVAL;

	}



	amdgpu_ras_parse_status_code(adev,

				     "inject",

				     ras_block_str(info->head.block),

				     (enum ta_ras_status)ret);

	if (ret)

		dev_err(adev->dev, "ras inject %s failed %d\n",

			ras_block_str(info->head.block), ret);



	return ret;

}