Add check passes
Fix all test cases
Add chirrtl support
Test with real RTL
Add optimization passes
Figure out naming
Convert to scala
Tech Report
ROM node


Support ASIC backend
   Pass to generate writemasks for ram's in general (ASICs and FPGAs)
     Mem of vec, should just work?
   ASIC rams (pass to replace smem with black box)
   Readwrite Port
Add %s, %b, %e etc. to spec

================================================
========== ADAM's BIG ARSE TODO LIST ============
================================================

======== Current Tasks ========
don't split on asuint and assint, and no need to emit cast of $unsigned
put clocks on accessors
add clock check to high firrtl check

naming still doesn't work - x!0 will conflict with x
think about inferring read enable from lo firrtl

Tests:
   Lowering for instance types with bundle ports
   More prefix tests
   Expand-when semantics
   Ensure module names are unique
   Large width of dshl

fix expand-whens to have correct semantics
need an annotation example
move width inference earlier (required for consistent vec width inference)
Temp elimination needs to count # uses
Check for recursively defined instances
Names in bundles must be unique
Fix reset scope
Scaling
Adam, could you add the following to firrtl (the program)
 - exit(0) on success, exit(1) on any failure
 - a “-“ as a file indicates stdin for input or stdout for output so:
    firrtl -i - -o - fir -X flo
 operates like a filter.
 - and we should also support:
    firrtl -X flo < foo.fir > foo.flo
 (another more common filter form).

======== Verilog Backend Notes ========
* 1) Emit module. No Parameters. Include clk and reset signals
o 2) Emit all declarations (wires,regs)
o 3) Initialize all regs with random values under synthesis
o 4) Emit all connections as assign statements
o 5) Emit assertions under always @ posedge clk, under synthesis
o 6) Emit all register updates:
      if(io_update_valid) begin
         R4 <= io_update_bits_target;
      end
   Note: muxes turn into if/else statements within the always@ block
Notes:
   For now, emit mems as reg with nothing else.
   WritePorts?
Checks:
   names in fields should be special renamed
   widths are -1 of size
   zero width?

======== Update Core ==========
Add RdWrPort

======== Check Passes ==========
High-Firrtl
   No combinational loops
   Clocks are used correctly

After adding dynamic assertions, insert bounds check with accessor expansion
Width inference
   No names
   No Unknowns
   All widths are positive, and nonzero
   Pad's width is greater than value's width
   pad's width is greater than value's width
   connect can connect from big to small?? <- I think this shouldn't be allowed
Width pad check?

======== Other Passes ========
constant folding (partial eval) pass
   Get rid of unnecessary pads
   push pad into literal
common subexpression elimination pass
deadcode elimination

======== Consultations ========
Andrew: Way to keep Array information for backends to avoid code explosion

======== Think About ========
verilog style guide
annotation system
zero-width wires
expanding mems (consider changing defmem to be size, and element type)
Multi-streams for print statements/asserts (Jack)
Consider def female node. (Patrick) 
Add FIFOs to the IR (Palmer)
Union Types
Enums?
Convert to scala
Firrtl interpreter (in scala)

======== Update Spec ========
Add explanation of an instance type, ie converting from input/output to default/reverse
   also, can only be used on the right side of :=
Write a better conditional section
Improve node section
Add priority of connect statements to spec
Use source/sink instead of input/output
Add assert statement explanation
think about printfs
think about subword on accessors, non-ground types
think about mems in lowered form - change ReadPort's reference to mem to be either exp or id
think about ROMS
think about how widths propagate - add section explicitly addressing this

FIRRTL rule: No name can be a prefix of any other name.
Future questions to address in spec:
   Introduction – motivation, and intended usage
   Philosophical justifications for all constructs
   More introduction for types, e.g. what is a ground type?
   What is a statement? What is an expression? What is a memory? Difference between vector type and memory? What are accessors for?
   Why would I ever write an empty statement? Mainly for use by compiler/passes
   What is a structural element? Duplication?
   Subtracting two unsigned numbers… Should talk to a math guy to figure it out
   What are shift left and shift right operations? HW doesn’t have these concepts. Need justification.
   What is lowered form? What is it for?

======== Pass Ideas ==========
Bounds checks for accessors
Overflow checks for add/add-wrap
Check combinational
Fast C++ where wires/register/instances are predicated
Verilog backend - put stuff in posedge clock, not assign statements, for speedup
Annotate mems with location stuff
Coverage tests, such as statespace or specific instances (like asserts, sort of)
   check all predicates of whens
Generate a ROM, and index with cycle counter, and dynamically check any wire on a given cycle

======== FIRRTL++ =========
Variable size FIFOs
TruthTable node
Custom types? Parameterized Types?
Priority encoder/Log2 nodes

======== Next Layer Components =======
Accelerator with config registers
Schedulable
   Decouple
   Nack
Scheduler

======== Notes ========
Which ones
Treat everything as just bits - the only operators that should exist are ones that emit different bits
Go through all primops with Andrew
